On 9/1/20 3:38 AM, Bin Meng wrote: > From: Bin Meng <bin.m...@windriver.com> > > Now that we have the newly introduced 'resetvec' property in the > RISC-V CPU and HART, instead of hard-coding the reset vector addr > in the CPU's instance_init(), move that to riscv_cpu_realize() > based on the configured property value from the RISC-V machines. > > Signed-off-by: Bin Meng <bin.m...@windriver.com> > Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> > --- > > (no changes since v1) > > hw/riscv/opentitan.c | 1 + > hw/riscv/sifive_e.c | 1 + > hw/riscv/sifive_u.c | 2 ++ > target/riscv/cpu.c | 7 ++----- > 4 files changed, 6 insertions(+), 5 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
