From: Frank Chang <frank.ch...@sifive.com> Signed-off-by: Frank Chang <frank.ch...@sifive.com> --- target/riscv/cpu.c | 8 ++++---- target/riscv/cpu.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 871c2ddfa1..6168166e64 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -340,7 +340,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) CPURISCVState *env = &cpu->env; RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); int priv_version = PRIV_VERSION_1_11_0; - int vext_version = VEXT_VERSION_0_07_1; + int vext_version = VEXT_VERSION_0_09_0; target_ulong target_misa = 0; Error *local_err = NULL; @@ -456,8 +456,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } if (cpu->cfg.vext_spec) { - if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) { - vext_version = VEXT_VERSION_0_07_1; + if (!g_strcmp0(cpu->cfg.vext_spec, "v0.9")) { + vext_version = VEXT_VERSION_0_09_0; } else { error_setg(errp, "Unsupported vector spec version '%s'", @@ -466,7 +466,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } } else { qemu_log("vector verison is not specified, " - "use the default value v0.7.1\n"); + "use the default value v0.9\n"); } set_vext_version(env, vext_version); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8b4a370572..18015f0bc0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -81,7 +81,7 @@ enum { #define PRIV_VERSION_1_10_0 0x00011000 #define PRIV_VERSION_1_11_0 0x00011100 -#define VEXT_VERSION_0_07_1 0x00000701 +#define VEXT_VERSION_0_09_0 0x00000900 #define TRANSLATE_PMP_FAIL 2 #define TRANSLATE_FAIL 1 -- 2.17.1