On Tue, 23 Jun 2020 at 20:37, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> This "bit" is a particular value of the page's MemAttr.
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> v6: Test HCR_EL2.{DC,DCT}; test Stage2 attributes.
> v8: Fill in cacheattrs for S1 disabled; retain tagging when
> combining attributes; set mte_tagging in arm_cpu_tlb_fill.
> ---
> target/arm/helper.c | 48 ++++++++++++++++++++++++++++++++++++++---
> target/arm/tlb_helper.c | 5 +++++
> 2 files changed, 50 insertions(+), 3 deletions(-)
> + } else if (access_type == MMU_INST_FETCH) {
> + if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
> + memattr = 0xee; /* Normal, WT, RA, NT */
> + } else {
> + memattr = 0x44; /* Normal, NC, No */
> + }
> + cacheattrs->shareability = 2; /* outersharable */
"outer shareable"
Otherwise
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
thanks
-- PMM
