Added Linux SMP support for the Xilinx Zynq platform (2x CPUs are
supported)
Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
---
Changed from v3:
Author reset
s/zynq_cpus/cpus
simplified custom secondary bootloader
Rebased
Changed from v2:
macro defined the maximum number of CPUS
Changed from v1:
Addressed PMM review
Shorted secondary bootloop using MVN instruction.
Used default reset secondary instead of custom one.
Rebased against QOM cpu developments.
Few whitespace fixes.
hw/arm/xilinx_zynq.c | 69 ++++++++++++++++++++++++++++++++++++++++------------
1 file changed, 53 insertions(+), 16 deletions(-)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 17251c7..c09ff36 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -27,6 +27,8 @@
#include "hw/ssi.h"
#include "qemu/error-report.h"
+#define MAX_CPUS 2
+
#define NUM_SPI_FLASHES 4
#define NUM_QSPI_FLASHES 2
#define NUM_QSPI_BUSSES 2
@@ -38,10 +40,37 @@
#define MPCORE_PERIPHBASE 0xF8F00000
+/* Dummy bootreg addr to keep ARM bootloader happy. Very top of OCM */
+#define SMP_BOOTREG_ADDR 0xfffffffc
+/* Put SMP bootloader up top of OCM under bootreg */
+#define SMP_BOOT_ADDR (SMP_BOOTREG_ADDR - sizeof(zynq_smpboot))
+
static const int dma_irqs[8] = {
46, 47, 48, 49, 72, 73, 74, 75
};
+/* Entry point for secondary CPU. Zynq Linux SMP protocol is to just reset
+ * the secondary to unpen, so any infinite loop will do the trick. Use a WFI
+ * loop as that will cause the emulated CPU to halt (and remove itself from
+ * the work queue pending an interrupt that never comes).
+ */
+static uint32_t zynq_smpboot[] = {
+ 0xe320f003, /* wfi */
+ 0xeafffffd, /* b <b wfi> */
+};
+
+static void zynq_write_secondary_boot(ARMCPU *cpu,
+ const struct arm_boot_info *info)
+{
+ int n;
+
+ for (n = 0; n < ARRAY_SIZE(zynq_smpboot); n++) {
+ zynq_smpboot[n] = tswap32(zynq_smpboot[n]);
+ }
+ rom_add_blob_fixed("smpboot", zynq_smpboot, sizeof(zynq_smpboot),
+ SMP_BOOT_ADDR);
+}
+
static struct arm_boot_info zynq_binfo = {};
static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
@@ -106,7 +135,7 @@ static void zynq_init(QEMUMachineInitArgs *args)
const char *kernel_cmdline = args->kernel_cmdline;
const char *initrd_filename = args->initrd_filename;
ObjectClass *cpu_oc;
- ARMCPU *cpu;
+ ARMCPU *cpu[MAX_CPUS];
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
@@ -122,17 +151,20 @@ static void zynq_init(QEMUMachineInitArgs *args)
}
cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
- cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc)));
+ for (n = 0; n < smp_cpus; n++) {
+ cpu[n] = ARM_CPU(object_new(object_class_get_name(cpu_oc)));
- object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
&err);
- if (err) {
- error_report("%s", error_get_pretty(err));
- exit(1);
- }
- object_property_set_bool(OBJECT(cpu), true, "realized", &err);
- if (err) {
- error_report("%s", error_get_pretty(err));
- exit(1);
+ object_property_set_int(OBJECT(cpu[n]), MPCORE_PERIPHBASE,
"reset-cbar",
+ &err);
+ if (err) {
+ error_report("%s", error_get_pretty(err));
+ exit(1);
+ }
+ object_property_set_bool(OBJECT(cpu[n]), true, "realized", &err);
+ if (err) {
+ error_report("%s", error_get_pretty(err));
+ exit(1);
+ }
}
/* max 2GB ram */
@@ -164,12 +196,14 @@ static void zynq_init(QEMUMachineInitArgs *args)
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000);
dev = qdev_create(NULL, "a9mpcore_priv");
- qdev_prop_set_uint32(dev, "num-cpu", 1);
+ qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
- sysbus_connect_irq(busdev, 0,
- qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
+ for (n = 0; n < smp_cpus; n++) {
+ sysbus_connect_irq(busdev, n,
+ qdev_get_gpio_in(DEVICE(cpu[n]), ARM_CPU_IRQ));
+ }
for (n = 0; n < 64; n++) {
pic[n] = qdev_get_gpio_in(dev, n);
@@ -233,7 +267,10 @@ static void zynq_init(QEMUMachineInitArgs *args)
zynq_binfo.kernel_filename = kernel_filename;
zynq_binfo.kernel_cmdline = kernel_cmdline;
zynq_binfo.initrd_filename = initrd_filename;
- zynq_binfo.nb_cpus = 1;
+ zynq_binfo.nb_cpus = smp_cpus;
+ zynq_binfo.write_secondary_boot = zynq_write_secondary_boot;
+ zynq_binfo.smp_loader_start = SMP_BOOT_ADDR;
+ zynq_binfo.smp_bootreg_addr = SMP_BOOTREG_ADDR;
zynq_binfo.board_id = 0xd32;
zynq_binfo.loader_start = 0;
arm_load_kernel(ARM_CPU(first_cpu), &zynq_binfo);
@@ -244,7 +281,7 @@ static QEMUMachine zynq_machine = {
.desc = "Xilinx Zynq Platform Baseboard for Cortex-A9",
.init = zynq_init,
.block_default_type = IF_SCSI,
- .max_cpus = 1,
+ .max_cpus = MAX_CPUS,
.no_sdcard = 1,
};
--
1.8.5.2
