Ping!
On Thu, Jan 2, 2014 at 5:30 PM, Peter Crosthwaite
<peter.crosthwa...@xilinx.com> wrote:
> Hi All,
>
> The clock controller module in the Zynq platform has the ability to halt
> and reset arbitrary devices, including the CPU. We use this feature to
> implement
> SMP Linux - the kernel halts CPU1 then rewrites the vector table to the
> secondary entry point and the resets+unhalts.
>
> This series adds SMP support to the Zynq machine, and patches the Zynq SLCR
> (the clock controller) to have DeviceState pointers to the CPUs. cpu_reset()
> is then called on the appropriate register access.
>
> Only the reset side is implemented (which is good enough for SMP linux
> as it stands). Future work is to implement the halting behaviour as
> well.
>
> changed since v3:
> Removed halting patches
> Reduced to minimal change needed for SMP Zynq
>
>
> Peter Crosthwaite (3):
> xilinx_zynq: added SMP support:
> zynq_slcr: Add links to the CPUs
> zynq_slcr: Implement CPU reset
>
> hw/arm/xilinx_zynq.c | 73
> ++++++++++++++++++++++++++++++++++++++++------------
> hw/misc/zynq_slcr.c | 23 +++++++++++++++++
> 2 files changed, 80 insertions(+), 16 deletions(-)
>
> --
> 1.8.5.2
>
