On 09/10/2012 04:09 PM, Maciej W. Rozycki wrote: > >> > No, this is about the PIC, not the CPU interrupt inputs. >> >> I see, the interrupt is still sent to the processor; but IRR reflects >> that status of the input line, not a "pending interrupt" status. > > Not really, this is still a "pending interrupt" status. > > For level-triggered inputs the state of IRR bits do indeed follow the > respective IRx inputs (taking the IMR into account). For edge-triggered > inputs the relevant IRR bit is set by a leading edge on its corresponding > IRx input and cleared when the interrupt is acknowledged (either with an > INTA bus cycle or by a data read bus cycle issued to the PIC armed with an > OCW3 that has had the POLL command bit set) OR with a trailing edge on IRx > (again, all this takes the IMR into account). At this point another > leading edge is required for the IRR bit to be set again, that is merely > keeping the IRx input's level active won't trigger another interrupt.
Ok, thanks, that explains it for me. -- error compiling committee.c: too many arguments to function
