On 2012-09-10 10:56, Avi Kivity wrote: > On 09/10/2012 04:27 AM, Matthew Ogilvie wrote: >> Intel's definition of "edge triggered" means: "asserted with a >> low-to-high transition at the time an interrupt is registered and >> then kept high until the interrupt is served via one of the >> EOI mechanisms or goes away unhandled." >> >> So the only difference between edge triggered and level triggered >> is in the leading edge, with no difference in the trailing edge. > > Hard to believe. So an edge while cpu interrupts are disabled is ignored?
No, this is about the PIC, not the CPU interrupt inputs. Matthew, did you verify this on real hardware by reading back the IRR as I suggested? Jan
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