On 2012-09-11 06:32, Matthew Ogilvie wrote: > On Mon, Sep 10, 2012 at 11:09:27AM +0200, Jan Kiszka wrote: >> On 2012-09-10 10:56, Avi Kivity wrote: >>> On 09/10/2012 04:27 AM, Matthew Ogilvie wrote: >>>> Intel's definition of "edge triggered" means: "asserted with a >>>> low-to-high transition at the time an interrupt is registered and >>>> then kept high until the interrupt is served via one of the >>>> EOI mechanisms or goes away unhandled." >>>> >>>> So the only difference between edge triggered and level triggered >>>> is in the leading edge, with no difference in the trailing edge. >>> >>> Hard to believe. So an edge while cpu interrupts are disabled is ignored? >> >> No, this is about the PIC, not the CPU interrupt inputs. >> >> Matthew, did you verify this on real hardware by reading back the IRR as >> I suggested? >> >> Jan > > I hadn't before, but now that I've checked, it's as expected: > > ----------- > Real hardware [Pentium 4]: > > cmdRead unmask IRR=4005 mask IRR=4001 sti unmask irq14 IRR=0001 DONE > > [I also see a final IRR=0000 occasionally. Probably just happened to > ask it while the timer (IRQ0) line is low (without the new understanding > of the trailing edge of an edge triggered interrupt, this would > have been confusing). I have most IRQ's (including > timer) masked off.] > > ----------- > Unpatched qemu: > > cmdRead unmask IRR=4015 mask IRR=4015 sti irq15 unmask IRR=4015 DONE > > [Presumably IRQ4 (0x10 - qemu's serial device model?) had a transient > edge during initialization, but had been masked off even before I > masked it off?] > > ----------- > Patched qemu: > > cmdRead unmask IRR=4005 mask IRR=4001 sti unmask irq14 IRR=0001 DONE >
I think this is convincing, maybe worth documenting in the related changelogs of QEMU and KVM. Avi, doubts remaining? Jan
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