On 09/10/2012 04:27 AM, Matthew Ogilvie wrote: > Intel's definition of "edge triggered" means: "asserted with a > low-to-high transition at the time an interrupt is registered and > then kept high until the interrupt is served via one of the > EOI mechanisms or goes away unhandled." > > So the only difference between edge triggered and level triggered > is in the leading edge, with no difference in the trailing edge.
Hard to believe. So an edge while cpu interrupts are disabled is ignored? > > This bug manifested itself when the guest was Microport UNIX > System V/386 v2.1 (ca. 1987), because it would sometimes mask > off IRQ14 in the slave IMR after it had already been asserted. > The master would still try to deliver an interrupt even though > IRQ2 had dropped again, resulting in a spurious interupt > (IRQ15) and a panicked kernel. This is something else. It means that setting an edge must happen after IMR is cleared to be picked up. But this is not what the patch is doing. > > Signed-off-by: Matthew Ogilvie <mmogilvi_q...@miniinfo.net> > --- > > If you missed the previous thread about this, see > http://www.mail-archive.com/qemu-devel@nongnu.org/msg129071.html > > hw/i8259.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/hw/i8259.c b/hw/i8259.c > index 6587666..c011787 100644 > --- a/hw/i8259.c > +++ b/hw/i8259.c > @@ -157,6 +157,7 @@ static void pic_set_irq(void *opaque, int irq, int level) > } > s->last_irr |= mask; > } else { > + s->irr &= ~mask; > s->last_irr &= ~mask; > } > } > -- error compiling committee.c: too many arguments to function
