On 10. 6. 25. 09:34, Philippe Mathieu-Daudé wrote:
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>
> Hi,
>
> On 2/6/25 15:12, Djordje Todorovic wrote:
>> This is needed for riscv based CPUs by MIPS.
>
> This justification is not really convincing.
>
>>
>> Signed-off-by: Chao-ying Fu <c...@mips.com>
>> Signed-off-by: Djordje Todorovic <djordje.todoro...@htecgroup.com>
>> ---
>> hw/intc/riscv_aclint.c | 33 +++++++++++++++++++++++++++++++--
>> hw/intc/riscv_aplic.c | 10 +++++++---
>> 2 files changed, 38 insertions(+), 5 deletions(-)
>>
>> diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
>> index b0139f03f5..5bda02a179 100644
>> --- a/hw/intc/riscv_aclint.c
>> +++ b/hw/intc/riscv_aclint.c
>> @@ -131,6 +131,9 @@ static uint64_t riscv_aclint_mtimer_read(void
>> *opaque, hwaddr addr,
>> size_t hartid = mtimer->hartid_base +
>> ((addr - mtimer->timecmp_base) >> 3);
>> CPUState *cpu = cpu_by_arch_id(hartid);
>> + if (cpu == NULL) {
>> + return 0;
>
> It looks like some misconfiguration. How do you reach that?
> Otherwise please log as GUEST_ERROR.
>
You are right, at the latest, it does not trigger those.
I will remove it in v3.
Thanks!
>> + }
>> CPURISCVState *env = cpu ? cpu_env(cpu) : NULL;
>> if (!env) {
>> qemu_log_mask(LOG_GUEST_ERROR,
>> @@ -174,6 +177,9 @@ static void riscv_aclint_mtimer_write(void
>> *opaque, hwaddr addr,
>> size_t hartid = mtimer->hartid_base +
>> ((addr - mtimer->timecmp_base) >> 3);
>> CPUState *cpu = cpu_by_arch_id(hartid);
>> + if (cpu == NULL) {
>
> If so, please log:
>
> qemu_log_mask(LOG_GUEST_ERROR,
> "aclint-mtimer: invalid hartid: %zu", hartid);
>
>> + return;
>> + }
>> CPURISCVState *env = cpu ? cpu_env(cpu) : NULL;
>
> Then env is valid, so this line needs update.
