On 2/6/25 15:12, Djordje Todorovic wrote:
The board model supports up to 64 harts with MIPS CPS, MIPS GCR, MIPS CPC, AIA plic, and AIA clint devices. The model can create boot code, if there is no -bios parameter. We can specify -smp x, cores=y,thread=z. Ex: Use 4 cores and 2 threads with each core to have 8 smp cpus as follows. qemu-system-riscv64 -cpu mips-p8700,resetvec=0x1fc00000 \ -m 2G -M boston-aia \ -smp 8,cores=4,threads=2 -kernel fw_payload.bin \ -drive file=rootfs.ext2,format=raw -serial stdio
Please add documentation in docs/system/riscv/ and link it in docs/system/target-riscv.rst.
Signed-off-by: Chao-ying Fu <c...@mips.com> Signed-off-by: Djordje Todorovic <djordje.todoro...@htecgroup.com> --- configs/devices/riscv64-softmmu/default.mak | 1 + hw/misc/Kconfig | 5 + hw/misc/meson.build | 1 + hw/misc/riscv_cmgcr.c | 204 +++++++++ hw/misc/riscv_cpc.c | 225 +++++++++ hw/riscv/Kconfig | 6 + hw/riscv/boston-aia.c | 484 ++++++++++++++++++++ hw/riscv/cps.c | 187 ++++++++ hw/riscv/meson.build | 1 + include/hw/misc/riscv_cmgcr.h | 77 ++++ include/hw/misc/riscv_cpc.h | 69 +++ include/hw/riscv/cps.h | 75 +++ 12 files changed, 1335 insertions(+) create mode 100644 hw/misc/riscv_cmgcr.c create mode 100644 hw/misc/riscv_cpc.c create mode 100644 hw/riscv/boston-aia.c create mode 100644 hw/riscv/cps.c create mode 100644 include/hw/misc/riscv_cmgcr.h create mode 100644 include/hw/misc/riscv_cpc.h create mode 100644 include/hw/riscv/cps.h
