On Tue, Jun 10, 2025 at 5:42 PM Philippe Mathieu-Daudé
<phi...@linaro.org> wrote:
>
> On 2/6/25 15:12, Djordje Todorovic wrote:
> > Define MIPS CSRs used for P8700 CPU.
> >
> > Signed-off-by: Chao-ying Fu <c...@mips.com>
> > Signed-off-by: Djordje Todorovic <djordje.todoro...@htecgroup.com>
> > ---
> > target/riscv/cpu.c | 3 +
> > target/riscv/cpu.h | 7 ++
> > target/riscv/meson.build | 1 +
> > target/riscv/mips_csr.c | 219 +++++++++++++++++++++++++++++++++++++++
> > 4 files changed, 230 insertions(+)
> > create mode 100644 target/riscv/mips_csr.c
>
>
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index c0e048a66d..984f93dd4a 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -497,6 +497,10 @@ struct CPUArchState {
> > target_ulong rnmip;
> > uint64_t rnmi_irqvec;
> > uint64_t rnmi_excpvec;
> > +
> > + uint64_t mipstvec; /* MIPS tvec register */
> > + uint64_t mipsconfig[12]; /* MIPS config register */
> > + uint64_t mipspmacfg[15]; /* MIPS pmacfg register */
>
> Pointless comments (not helpful at all).
>
> Alternatively:
>
> struct {
> uint64_t tvec;
> uint64_t config[12];
> uint64_t pmacfg[15];
> } mips;
We don't want to store these in the CPUArchState. So you will need to
create a vendor specific struct and you can then point to that from
CPUArchState, similar to the existing `RISCVCSR *custom_csrs`
Alistair
>
> > };
>
>
