Add a new function, so we can change reset vector from platforms.
Signed-off-by: Chao-ying Fu <c...@mips.com>
Signed-off-by: Djordje Todorovic <djordje.todoro...@htecgroup.com>
---
target/riscv/cpu.h | 2 ++
target/riscv/translate.c | 8 ++++++++
2 files changed, 10 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 229ade9ed9..c0e048a66d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -656,6 +656,8 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env,
target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
+void cpu_set_exception_base(int vp_index, target_ulong address);
+
FIELD(TB_FLAGS, MEM_IDX, 0, 3)
FIELD(TB_FLAGS, FS, 3, 2)
/* Vector flags */
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d7a6de02df..2cba1a26a7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1427,3 +1427,11 @@ void riscv_translate_init(void)
load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val),
"load_val");
}
+
+void cpu_set_exception_base(int vp_index, target_ulong address)
+{
+#ifndef CONFIG_USER_ONLY
+ RISCVCPU *vp = RISCV_CPU(qemu_get_cpu(vp_index));
+ vp->env.resetvec = address;
+#endif
+}
--
2.34.1
