This patch series adds support for MIPS P8700 CPU based on RISC-V. The P8700 is a high-performance processor from MIPS designed to meet the demands of modern workloads, offering exceptional scalability and efficiency. It builds on MIPS's established architectural strengths while introducing enhancements that set it apart. For more details, you can check out the official product page here: https://mips.com/products/hardware/p8700/.
Djordje Todorovic (9): hw/intc: Allow gaps in hartids for aclint and aplic target/riscv: Add cpu_set_exception_base target/riscv: Add MIPS P8700 CPU target/riscv: Add MIPS P8700 CSRs target/riscv: Add mips.ccmov instruction target/riscv: Add mips.pref instruction target/riscv: Add Xmipslsp instructions configs/devices: Add MIPS Boston-aia board model to RISC-V hw/riscv: Add a network device e1000e to the boston-aia configs/devices/riscv64-softmmu/default.mak | 1 + hw/intc/riscv_aclint.c | 24 +- hw/intc/riscv_aplic.c | 9 +- hw/misc/Kconfig | 5 + hw/misc/meson.build | 1 + hw/misc/riscv_cmgcr.c | 203 ++++++++ hw/misc/riscv_cpc.c | 221 +++++++++ hw/pci/pci.c | 23 +- hw/riscv/Kconfig | 6 + hw/riscv/boston-aia.c | 484 ++++++++++++++++++++ hw/riscv/cps.c | 184 ++++++++ hw/riscv/meson.build | 1 + include/hw/misc/riscv_cmgcr.h | 75 +++ include/hw/misc/riscv_cpc.h | 66 +++ include/hw/riscv/cps.h | 72 +++ target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 39 ++ target/riscv/cpu.h | 9 + target/riscv/cpu_cfg.h | 8 + target/riscv/insn_trans/trans_xmips.c.inc | 136 ++++++ target/riscv/meson.build | 2 + target/riscv/mips_csr.c | 226 +++++++++ target/riscv/translate.c | 11 + target/riscv/xmips.decode | 39 ++ 24 files changed, 1830 insertions(+), 16 deletions(-) create mode 100644 hw/misc/riscv_cmgcr.c create mode 100644 hw/misc/riscv_cpc.c create mode 100644 hw/riscv/boston-aia.c create mode 100644 hw/riscv/cps.c create mode 100644 include/hw/misc/riscv_cmgcr.h create mode 100644 include/hw/misc/riscv_cpc.h create mode 100644 include/hw/riscv/cps.h create mode 100644 target/riscv/insn_trans/trans_xmips.c.inc create mode 100644 target/riscv/mips_csr.c create mode 100644 target/riscv/xmips.decode -- 2.34.1
