Add mips.ccmov defined by Xmipscmov.
Signed-off-by: Chao-ying Fu <c...@mips.com>
Signed-off-by: Djordje Todorovic <djordje.todoro...@htecgroup.com>
---
target/riscv/cpu.c | 3 ++
target/riscv/cpu_cfg.h | 6 ++++
target/riscv/insn_trans/trans_xmips.c.inc | 38 +++++++++++++++++++++++
target/riscv/meson.build | 1 +
target/riscv/translate.c | 3 ++
target/riscv/xmips.decode | 23 ++++++++++++++
6 files changed, 74 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_xmips.c.inc
create mode 100644 target/riscv/xmips.decode
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d22c1baf09..6d866253f5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -236,6 +236,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair),
ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync),
ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0,
ext_XVentanaCondOps),
+ ISA_EXT_DATA_ENTRY(xmipscmov, PRIV_VERSION_1_12_0, ext_xmipscmov),
{ },
};
@@ -540,6 +541,7 @@ static void rv64_mips_p8700_cpu_init(Object *obj)
cpu->cfg.pmp = true;
cpu->cfg.ext_zba = true;
cpu->cfg.ext_zbb = true;
+ cpu->cfg.ext_xmipscmov = true;
cpu->cfg.marchid = 0x8000000000000201;
}
@@ -1756,6 +1758,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false),
MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false),
MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false),
+ MULTI_EXT_CFG_BOOL("xmipscmov", ext_xmipscmov, false),
{ },
};
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 8a843482cc..e6cce7fdf8 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -182,6 +182,7 @@ struct RISCVCPUConfig {
bool ext_xtheadmempair;
bool ext_xtheadsync;
bool ext_XVentanaCondOps;
+ bool ext_xmipscmov;
uint32_t pmu_mask;
uint16_t vlenb;
@@ -210,6 +211,11 @@ static inline bool always_true_p(const RISCVCPUConfig *cfg
__attribute__((__unus
return true;
}
+static inline bool has_xmips_p(const RISCVCPUConfig *cfg)
+{
+ return cfg->ext_xmipscmov;
+}
+
static inline bool has_xthead_p(const RISCVCPUConfig *cfg)
{
return cfg->ext_xtheadba || cfg->ext_xtheadbb ||
diff --git a/target/riscv/insn_trans/trans_xmips.c.inc
b/target/riscv/insn_trans/trans_xmips.c.inc
new file mode 100644
index 0000000000..a555c94e23
--- /dev/null
+++ b/target/riscv/insn_trans/trans_xmips.c.inc
@@ -0,0 +1,38 @@
+/*
+ * RISC-V translation routines for the MIPS extensions (xmips*).
+ *
+ * Copyright (c) 2025 MIPS
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2.1 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_XMIPSCMOV(ctx) do { \
+ if (!ctx->cfg_ptr->ext_xmipscmov) { \
+ return false; \
+ } \
+} while (0)
+
+static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a)
+{
+ REQUIRE_XMIPSCMOV(ctx);
+
+ TCGv zero, source1, source2, source3;
+ zero = tcg_constant_tl(0);
+ source1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ source2 = get_gpr(ctx, a->rs2, EXT_NONE);
+ source3 = get_gpr(ctx, a->rs3, EXT_NONE);
+
+ tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[a->rd], source2, zero, source1,
source3);
+
+ return true;
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index fbb6c8fb45..26cd11ec00 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -4,6 +4,7 @@ gen = [
decodetree.process('insn32.decode', extra_args:
'--static-decode=decode_insn32'),
decodetree.process('xthead.decode', extra_args:
'--static-decode=decode_xthead'),
decodetree.process('XVentanaCondOps.decode', extra_args:
'--static-decode=decode_XVentanaCodeOps'),
+ decodetree.process('xmips.decode', extra_args:
'--static-decode=decode_xmips'),
]
riscv_ss = ss.source_set()
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 2b8ddd184f..0dcb9c0a49 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1195,8 +1195,10 @@ static uint32_t opcode_at(DisasContextBase *dcbase,
target_ulong pc)
#include "insn_trans/trans_svinval.c.inc"
#include "insn_trans/trans_rvbf16.c.inc"
#include "decode-xthead.c.inc"
+#include "decode-xmips.c.inc"
#include "insn_trans/trans_xthead.c.inc"
#include "insn_trans/trans_xventanacondops.c.inc"
+#include "insn_trans/trans_xmips.c.inc"
/* Include the auto-generated decoder for 16 bit insn */
#include "decode-insn16.c.inc"
@@ -1217,6 +1219,7 @@ static inline int insn_len(uint16_t first_word)
const RISCVDecoder decoder_table[] = {
{ always_true_p, decode_insn32 },
+ { has_xmips_p, decode_xmips},
{ has_xthead_p, decode_xthead},
{ has_XVentanaCondOps_p, decode_XVentanaCodeOps},
};
diff --git a/target/riscv/xmips.decode b/target/riscv/xmips.decode
new file mode 100644
index 0000000000..94d37c10ae
--- /dev/null
+++ b/target/riscv/xmips.decode
@@ -0,0 +1,23 @@
+#
+# RISC-V translation routines for the MIPS extension
+#
+# Copyright (c) 2025 MIPS
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference: MIPS P8700 instructions
+# (https://mips.com/products/hardware/p8700/)
+
+# Fields
+%rs3 27:5
+%rs2 20:5
+%rs1 15:5
+%rd 7:5
+
+# Argument sets
+
+# Formats
+@r4 ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rd
+
+# *** RV64 MIPS Extension ***
+ccmov .....11 ..... ..... 011 ..... 0001011 @r4
--
2.34.1
