[PATCH 6/9] target/riscv: Add mips.pref instruction

[Djordje Todorovic]

Add MIPS P8700 prefetch instruction defined by Xmipscbop.

Signed-off-by: Chao-ying Fu <c...@mips.com>
Signed-off-by: Djordje Todorovic <djordje.todoro...@htecgroup.com>
---
 target/riscv/cpu.c                        |  3 +++
 target/riscv/cpu_cfg.h                    |  3 ++-
 target/riscv/insn_trans/trans_xmips.c.inc | 14 ++++++++++++++
 target/riscv/xmips.decode                 |  4 ++++
 4 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6d866253f5..d201a0dd02 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -236,6 +236,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair),
     ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync),
     ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, 
ext_XVentanaCondOps),
+    ISA_EXT_DATA_ENTRY(xmipscbop, PRIV_VERSION_1_12_0, ext_xmipscbop),
     ISA_EXT_DATA_ENTRY(xmipscmov, PRIV_VERSION_1_12_0, ext_xmipscmov),
 
     { },
@@ -541,6 +542,7 @@ static void rv64_mips_p8700_cpu_init(Object *obj)
     cpu->cfg.pmp = true;
     cpu->cfg.ext_zba = true;
     cpu->cfg.ext_zbb = true;
+    cpu->cfg.ext_xmipscbop = true;
     cpu->cfg.ext_xmipscmov = true;
     cpu->cfg.marchid = 0x8000000000000201;
 }
@@ -1758,6 +1760,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
     MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false),
     MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false),
     MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false),
+    MULTI_EXT_CFG_BOOL("xmipscbop", ext_xmipscbop, false),
     MULTI_EXT_CFG_BOOL("xmipscmov", ext_xmipscmov, false),
 
     { },
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index e6cce7fdf8..9643625018 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -182,6 +182,7 @@ struct RISCVCPUConfig {
     bool ext_xtheadmempair;
     bool ext_xtheadsync;
     bool ext_XVentanaCondOps;
+    bool ext_xmipscbop;
     bool ext_xmipscmov;
 
     uint32_t pmu_mask;
@@ -213,7 +214,7 @@ static inline bool always_true_p(const RISCVCPUConfig *cfg 
__attribute__((__unus
 
 static inline bool has_xmips_p(const RISCVCPUConfig *cfg)
 {
-    return cfg->ext_xmipscmov;
+    return cfg->ext_xmipscbop || cfg->ext_xmipscmov;
 }
 
 static inline bool has_xthead_p(const RISCVCPUConfig *cfg)
diff --git a/target/riscv/insn_trans/trans_xmips.c.inc 
b/target/riscv/insn_trans/trans_xmips.c.inc
index a555c94e23..375970defc 100644
--- a/target/riscv/insn_trans/trans_xmips.c.inc
+++ b/target/riscv/insn_trans/trans_xmips.c.inc
@@ -16,6 +16,12 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#define REQUIRE_XMIPSCBOP(ctx) do {              \
+    if (!ctx->cfg_ptr->ext_xmipscbop) {          \
+        return false;                            \
+    }                                            \
+} while (0)
+
 #define REQUIRE_XMIPSCMOV(ctx) do {              \
     if (!ctx->cfg_ptr->ext_xmipscmov) {          \
         return false;                            \
@@ -36,3 +42,11 @@ static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a)
 
     return true;
 }
+
+static bool trans_pref(DisasContext *ctx, arg_pref *a)
+{
+    REQUIRE_XMIPSCBOP(ctx);
+
+    /* Nop */
+    return true;
+}
diff --git a/target/riscv/xmips.decode b/target/riscv/xmips.decode
index 94d37c10ae..56237fe610 100644
--- a/target/riscv/xmips.decode
+++ b/target/riscv/xmips.decode
@@ -13,11 +13,15 @@
 %rs2       20:5
 %rs1       15:5
 %rd        7:5
+%imm_9     20:9
+%imm_hint  7:5
 
 # Argument sets
 
 # Formats
+@r1_pref ...   ......... ..... ... ..... ....... %imm_9 %rs1 %imm_hint
 @r4      ..... ..  ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rd
 
 # *** RV64 MIPS Extension ***
 ccmov       .....11  ..... ..... 011 .....  0001011 @r4
+pref        000  ......... ..... 000 .....  0001011 @r1_pref
-- 
2.34.1