Start putting all the CPU definitions in a struct. Later this will replace
instance_init functions with declarative code, for now just remove the
ugly cast of class_data.
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
---
target/riscv/cpu.h | 4 ++++
target/riscv/cpu.c | 26 +++++++++++++++++---------
2 files changed, 21 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 97713681cbe..b2c9302634d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -517,6 +517,10 @@ struct ArchCPU {
const GPtrArray *decoders;
};
+typedef struct RISCVCPUDef {
+ RISCVMXL misa_mxl_max; /* max mxl for this cpu */
+} RISCVCPUDef;
+
/**
* RISCVCPUClass:
* @parent_realize: The parent class' realize handler.
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ed9da692030..29cfae38b75 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2955,7 +2955,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void
*data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
- mcc->misa_mxl_max = (uint32_t)(uintptr_t)data;
+ mcc->misa_mxl_max = ((RISCVCPUDef *)data)->misa_mxl_max;
riscv_cpu_validate_misa_mxl(mcc);
}
@@ -3051,40 +3051,48 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char
*nodename)
}
#endif
-#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max, initfn) \
+#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max_, initfn) \
{ \
.name = (type_name), \
.parent = TYPE_RISCV_DYNAMIC_CPU, \
.instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
- .class_data = (void *)(misa_mxl_max) \
+ .class_data = &((RISCVCPUDef) { \
+ .misa_mxl_max = (misa_mxl_max_), \
+ }), \
}
-#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max, initfn) \
+#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max_, initfn) \
{ \
.name = (type_name), \
.parent = TYPE_RISCV_VENDOR_CPU, \
.instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
- .class_data = (void *)(misa_mxl_max) \
+ .class_data = &((RISCVCPUDef) { \
+ .misa_mxl_max = (misa_mxl_max_), \
+ }), \
}
-#define DEFINE_BARE_CPU(type_name, misa_mxl_max, initfn) \
+#define DEFINE_BARE_CPU(type_name, misa_mxl_max_, initfn) \
{ \
.name = (type_name), \
.parent = TYPE_RISCV_BARE_CPU, \
.instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
- .class_data = (void *)(misa_mxl_max) \
+ .class_data = &((RISCVCPUDef) { \
+ .misa_mxl_max = (misa_mxl_max_), \
+ }), \
}
-#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max, initfn) \
+#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max_, initfn) \
{ \
.name = (type_name), \
.parent = TYPE_RISCV_BARE_CPU, \
.instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
- .class_data = (void *)(misa_mxl_max) \
+ .class_data = &((RISCVCPUDef) { \
+ .misa_mxl_max = (misa_mxl_max_), \
+ }), \
}
static const TypeInfo riscv_cpu_type_infos[] = {
--
2.48.1
