Re: [PATCH 02/22] target/riscv: introduce RISCVCPUDef

[Philippe Mathieu-Daudé]

On 9/2/25 19:44, Philippe Mathieu-Daudé wrote:

On 6/2/25 22:16, Richard Henderson wrote:

It would be nice if this were const, i.e.

   .class_data = (void *) &(const RISCVCPUDef){
       ...
   },

This will in fact create an anonymous object in .rodata.

We have other uses that do the extra casting away const,
e.g. armsse_variants in hw/arm/armsse.c.  Although I suspect
*all* usage of .class_init can and should be with const data.

The only non-const use I noticed is Xtensa:

static void xtensa_finalize_config(XtensaConfig *config)
{
     if (config->isa_internal) {
         init_libisa(config);
     }

     if (config->gdb_regmap.num_regs == 0 ||
         config->gdb_regmap.num_core_regs == 0) {
         unsigned n_regs = 0;
         unsigned n_core_regs = 0;

         xtensa_count_regs(config, &n_regs, &n_core_regs);
         if (config->gdb_regmap.num_regs == 0) {
             config->gdb_regmap.num_regs = n_regs;
         }
         if (config->gdb_regmap.num_core_regs == 0) {
             config->gdb_regmap.num_core_regs = n_core_regs;
         }
     }
}

static void xtensa_core_class_init(ObjectClass *oc, void *data)
{
     CPUClass *cc = CPU_CLASS(oc);
     XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc);
     XtensaConfig *config = data;

     xtensa_finalize_config(config);
     ...

Which I suppose can be fixed by calling xtensa_finalize_config()
somewhere within the class register:

void xtensa_register_core(XtensaConfigList *node)
{
    TypeInfo type = {
        .parent = TYPE_XTENSA_CPU,
        .class_init = xtensa_core_class_init,
        .class_data = (void *)node->config,
    };