They are never accessed together with the rest of the CPUConfig data,
so just store it in the ArchCPU struct.
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
---
target/riscv/cpu.h | 16 +++++++++
target/riscv/cpu_cfg.h | 16 ---------
target/riscv/cpu_cfg_fields.h.inc | 8 -----
hw/riscv/virt-acpi-build.c | 6 ++--
hw/riscv/virt.c | 4 +--
target/riscv/cpu.c | 56 +++++++++++++++----------------
target/riscv/csr.c | 2 +-
target/riscv/tcg/tcg-cpu.c | 2 +-
8 files changed, 50 insertions(+), 60 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 00ec475fbba..7f6c4fd138c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -492,6 +492,21 @@ struct CPUArchState {
uint64_t rnmi_excpvec;
};
+/*
+ * map is a 16-bit bitmap: the most significant set bit in map is the maximum
+ * satp mode that is supported. It may be chosen by the user and must respect
+ * what qemu implements (valid_1_10_32/64) and what the hw is capable of
+ * (supported bitmap below).
+ *
+ * init is a 16-bit bitmap used to make sure the user selected a correct
+ * configuration as per the specification.
+ *
+ * supported is a 16-bit bitmap used to reflect the hw capabilities.
+ */
+typedef struct {
+ uint16_t map, init, supported;
+} RISCVSATPModes;
+
/*
* RISCVCPU:
* @env: #CPURISCVState
@@ -508,6 +523,7 @@ struct ArchCPU {
/* Configuration Settings */
RISCVCPUConfig cfg;
+ RISCVSATPModes satp_modes;
QEMUTimer *pmu_timer;
/* A bitmask of Available programmable counters */
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 07789a9de88..e9bf75730a6 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -21,25 +21,9 @@
#ifndef RISCV_CPU_CFG_H
#define RISCV_CPU_CFG_H
-/*
- * map is a 16-bit bitmap: the most significant set bit in map is the maximum
- * satp mode that is supported. It may be chosen by the user and must respect
- * what qemu implements (valid_1_10_32/64) and what the hw is capable of
- * (supported bitmap below).
- *
- * init is a 16-bit bitmap used to make sure the user selected a correct
- * configuration as per the specification.
- *
- * supported is a 16-bit bitmap used to reflect the hw capabilities.
- */
-typedef struct {
- uint16_t map, init, supported;
-} RISCVSATPMap;
-
struct RISCVCPUConfig {
#define BOOL_FIELD(x) bool x;
#define TYPED_FIELD(type, x) type x;
-#define STRUCT_FIELD(type, x) type x;
#include "cpu_cfg_fields.h.inc"
};
diff --git a/target/riscv/cpu_cfg_fields.h.inc
b/target/riscv/cpu_cfg_fields.h.inc
index cbedf0a703b..b8cadf02a4e 100644
--- a/target/riscv/cpu_cfg_fields.h.inc
+++ b/target/riscv/cpu_cfg_fields.h.inc
@@ -4,9 +4,6 @@
#ifndef TYPED_FIELD
#define TYPED_FIELD(type, x)
#endif
-#ifndef STRUCT_FIELD
-#define STRUCT_FIELD(type, x)
-#endif
BOOL_FIELD(ext_zba)
BOOL_FIELD(ext_zbb)
@@ -162,10 +159,5 @@ TYPED_FIELD(uint16_t, cbom_blocksize)
TYPED_FIELD(uint16_t, cbop_blocksize)
TYPED_FIELD(uint16_t, cboz_blocksize)
-#ifndef CONFIG_USER_ONLY
-STRUCT_FIELD(RISCVSATPMap, satp_mode)
-#endif
-
#undef BOOL_FIELD
#undef TYPED_FIELD
-#undef STRUCT_FIELD
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 1ad68005085..60e607d12ac 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -281,7 +281,7 @@ static void build_rhct(GArray *table_data,
num_rhct_nodes++;
}
- if (cpu->cfg.satp_mode.supported != 0) {
+ if (cpu->satp_modes.supported != 0) {
num_rhct_nodes++;
}
@@ -341,8 +341,8 @@ static void build_rhct(GArray *table_data,
}
/* MMU node structure */
- if (cpu->cfg.satp_mode.supported != 0) {
- satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
+ if (cpu->satp_modes.supported != 0) {
+ satp_mode_max = satp_mode_max_from_map(cpu->satp_modes.map);
mmu_offset = table_data->len - table.table_offset;
build_append_int_noprefix(table_data, 2, 2); /* Type */
build_append_int_noprefix(table_data, 8, 2); /* Length */
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 241389d72f8..41f0a9c4caf 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -251,8 +251,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int
socket,
s->soc[socket].hartid_base + cpu);
qemu_fdt_add_subnode(ms->fdt, cpu_name);
- if (cpu_ptr->cfg.satp_mode.supported != 0) {
- satp_mode_max = satp_mode_max_from_map(cpu_ptr->cfg.satp_mode.map);
+ if (cpu_ptr->satp_modes.supported != 0) {
+ satp_mode_max = satp_mode_max_from_map(cpu_ptr->satp_modes.map);
sv_name = g_strdup_printf("riscv,%s",
satp_mode_str(satp_mode_max, is_32_bit));
qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 006d8696216..d9f06e3f0c4 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -78,8 +78,6 @@ static void riscv_cpu_cfg_merge(RISCVCPUConfig *dest,
RISCVCPUConfig *src)
{
#define BOOL_FIELD(x) dest->x |= src->x;
#define TYPED_FIELD(type, x) if (src->x) dest->x = src->x;
- /* only satp_mode, which is initialized by instance_init */
-#define STRUCT_FIELD(type, x)
#include "cpu_cfg_fields.h.inc"
}
@@ -448,7 +446,7 @@ static void set_satp_mode_max_supported(RISCVCPU *cpu,
for (int i = 0; i <= satp_mode; ++i) {
if (valid_vm[i]) {
- cpu->cfg.satp_mode.supported |= (1 << i);
+ cpu->satp_modes.supported |= (1 << i);
}
}
}
@@ -463,11 +461,11 @@ static void set_satp_mode_default_map(RISCVCPU *cpu)
*/
if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_BARE_CPU) != NULL) {
warn_report("No satp mode set. Defaulting to 'bare'");
- cpu->cfg.satp_mode.map = (1 << VM_1_10_MBARE);
+ cpu->satp_modes.map = (1 << VM_1_10_MBARE);
return;
}
- cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported;
+ cpu->satp_modes.map = cpu->satp_modes.supported;
}
#endif
@@ -826,15 +824,15 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu,
Error **errp)
uint8_t satp_mode_map_max, satp_mode_supported_max;
/* The CPU wants the OS to decide which satp mode to use */
- if (cpu->cfg.satp_mode.supported == 0) {
+ if (cpu->satp_modes.supported == 0) {
return;
}
satp_mode_supported_max =
- satp_mode_max_from_map(cpu->cfg.satp_mode.supported);
+ satp_mode_max_from_map(cpu->satp_modes.supported);
- if (cpu->cfg.satp_mode.map == 0) {
- if (cpu->cfg.satp_mode.init == 0) {
+ if (cpu->satp_modes.map == 0) {
+ if (cpu->satp_modes.init == 0) {
/* If unset by the user, we fallback to the default satp mode. */
set_satp_mode_default_map(cpu);
} else {
@@ -844,11 +842,11 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu,
Error **errp)
* valid_vm_1_10_32/64.
*/
for (int i = 1; i < 16; ++i) {
- if ((cpu->cfg.satp_mode.init & (1 << i)) &&
- (cpu->cfg.satp_mode.supported & (1 << i))) {
+ if ((cpu->satp_modes.init & (1 << i)) &&
+ (cpu->satp_modes.supported & (1 << i))) {
for (int j = i - 1; j >= 0; --j) {
- if (cpu->cfg.satp_mode.supported & (1 << j)) {
- cpu->cfg.satp_mode.map |= (1 << j);
+ if (cpu->satp_modes.supported & (1 << j)) {
+ cpu->satp_modes.map |= (1 << j);
break;
}
}
@@ -858,7 +856,7 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu,
Error **errp)
}
}
- satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
+ satp_mode_map_max = satp_mode_max_from_map(cpu->satp_modes.map);
/* Make sure the user asked for a supported configuration (HW and qemu) */
if (satp_mode_map_max > satp_mode_supported_max) {
@@ -874,9 +872,9 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu,
Error **errp)
*/
if (!rv32) {
for (int i = satp_mode_map_max - 1; i >= 0; --i) {
- if (!(cpu->cfg.satp_mode.map & (1 << i)) &&
- (cpu->cfg.satp_mode.init & (1 << i)) &&
- (cpu->cfg.satp_mode.supported & (1 << i))) {
+ if (!(cpu->satp_modes.map & (1 << i)) &&
+ (cpu->satp_modes.init & (1 << i)) &&
+ (cpu->satp_modes.supported & (1 << i))) {
error_setg(errp, "cannot disable %s satp mode if %s "
"is enabled", satp_mode_str(i, false),
satp_mode_str(satp_mode_map_max, false));
@@ -887,8 +885,8 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu,
Error **errp)
/* Finally expand the map so that all valid modes are set */
for (int i = satp_mode_map_max - 1; i >= 0; --i) {
- if (cpu->cfg.satp_mode.supported & (1 << i)) {
- cpu->cfg.satp_mode.map |= (1 << i);
+ if (cpu->satp_modes.supported & (1 << i)) {
+ cpu->satp_modes.map |= (1 << i);
}
}
}
@@ -968,11 +966,11 @@ bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu)
static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
- RISCVSATPMap *satp_map = opaque;
+ RISCVSATPModes *satp_modes = opaque;
uint8_t satp = satp_mode_from_str(name);
bool value;
- value = satp_map->map & (1 << satp);
+ value = satp_modes->map & (1 << satp);
visit_type_bool(v, name, &value, errp);
}
@@ -980,7 +978,7 @@ static void cpu_riscv_get_satp(Object *obj, Visitor *v,
const char *name,
static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
- RISCVSATPMap *satp_map = opaque;
+ RISCVSATPModes *satp_modes = opaque;
uint8_t satp = satp_mode_from_str(name);
bool value;
@@ -988,8 +986,8 @@ static void cpu_riscv_set_satp(Object *obj, Visitor *v,
const char *name,
return;
}
- satp_map->map = deposit32(satp_map->map, satp, 1, value);
- satp_map->init |= 1 << satp;
+ satp_modes->map = deposit32(satp_modes->map, satp, 1, value);
+ satp_modes->init |= 1 << satp;
}
void riscv_add_satp_mode_properties(Object *obj)
@@ -998,16 +996,16 @@ void riscv_add_satp_mode_properties(Object *obj)
if (cpu->env.misa_mxl == MXL_RV32) {
object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp,
- cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
+ cpu_riscv_set_satp, NULL, &cpu->satp_modes);
} else {
object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp,
- cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
+ cpu_riscv_set_satp, NULL, &cpu->satp_modes);
object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp,
- cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
+ cpu_riscv_set_satp, NULL, &cpu->satp_modes);
object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp,
- cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
+ cpu_riscv_set_satp, NULL, &cpu->satp_modes);
object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp,
- cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
+ cpu_riscv_set_satp, NULL, &cpu->satp_modes);
}
}
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index afb7544f078..1000fe1f07f 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1862,7 +1862,7 @@ static RISCVException read_mstatus(CPURISCVState *env,
int csrno,
static bool validate_vm(CPURISCVState *env, target_ulong vm)
{
- uint64_t mode_supported = riscv_cpu_cfg(env)->satp_mode.map;
+ uint64_t mode_supported = env_archcpu(env)->satp_modes.map;
return get_field(mode_supported, (1 << vm));
}
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 46cd8032c79..d30d9f427ab 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -693,7 +693,7 @@ static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu,
RISCVCPUProfile *profile,
bool send_warn)
{
- int satp_max = satp_mode_max_from_map(cpu->cfg.satp_mode.supported);
+ int satp_max = satp_mode_max_from_map(cpu->satp_modes.supported);
if (profile->satp_mode > satp_max) {
if (send_warn) {
--
2.48.1
