On Wed, Oct 25, 2023 at 11:14:42AM -0400, Peter Xu wrote:
> On Wed, Oct 25, 2023 at 01:14:26PM +0800, Ethan Chen wrote:
> > Signed-off-by: Ethan Chen <etha...@andestech.com>
> > ---
> > system/physmem.c | 9 +++++++--
> > 1 file changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/system/physmem.c b/system/physmem.c
> > index fc2b0fee01..53b6ab735c 100644
> > --- a/system/physmem.c
> > +++ b/system/physmem.c
> > @@ -432,8 +432,13 @@ static MemoryRegionSection
> > address_space_translate_iommu(IOMMUMemoryRegion *iomm
> > iommu_idx = imrc->attrs_to_index(iommu_mr, attrs);
> > }
> >
> > - iotlb = imrc->translate(iommu_mr, addr, is_write ?
> > - IOMMU_WO : IOMMU_RO, iommu_idx);
> > + if (imrc->translate_size) {
> > + iotlb = imrc->translate_size(iommu_mr, addr, *plen_out,
> > is_write ?
> > + IOMMU_WO : IOMMU_RO, iommu_idx);
> > + } else {
> > + iotlb = imrc->translate(iommu_mr, addr, is_write ?
> > + IOMMU_WO : IOMMU_RO, iommu_idx);
> > + }
>
> Currently the translation size is encoded in iotlb.addr_mask. Can riscv do
> the same?
Riscv do the same, so translation size may be reduced by iotlb.addr_mask.
>
> For example, lookup addr in match_entry_md() ranges, report size back into
> iotlb.addr_mask, rather than enforcing *plen_out range always resides in
> one translation only.
>
> IMHO it's actually legal if *plen_out covers more than one IOMMU
> translations. QEMU memory core should have taken care of that by
> separately translate the ranges and apply RW on top. With current proposal
> of translate_size() I think it'll fail instead, which is not wanted.
>
My target is to support IOPMP partially hit error. IOPMP checks whole memory
access region is in the same entry. If not, reject the access instead of modify
the access size.
Because most of IOPMP permisson checking features can be implemented by
current IOMMU class, so I add this function in IOMMU class. There may be
other more suitable ways to support partially hit error.
> Thanks,
>
> --
> Peter Xu
>
Thanks,
Ethan Chen
