Add cc list. On Fri, Oct 27, 2023 at 12:02:24PM -0400, Peter Xu wrote: > On Fri, Oct 27, 2023 at 11:28:36AM +0800, Ethan Chen wrote: > > On Thu, Oct 26, 2023 at 10:20:41AM -0400, Peter Xu wrote: > > > Could you elaborate why is that important? In what use case? > > I was not involved in the formulation of the IOPMP specification, but I'll > > try > > to explain my perspective. IOPMP use the same the idea as PMP. "The > > matching > > PMP entry must match all bytes of an access, or the access fails." > > > > > > > > Consider IOVA mapped for address range iova=[0, 4K] only, here we have a > > > DMA request with range=[0, 8K]. Now my understanding is what you want to > > > achieve is don't trigger the DMA to [0, 4K] and fail the whole [0, 8K] > > > request. > > > > > > Can we just fail at the latter DMA [4K, 8K] when it happens? After all, > > > IIUC a device can split the 0-8K DMA into two smaller DMAs, then the 1st > > > chunk can succeed then if it falls in 0-4K. Some further explanation of > > > the failure use case could be helpful. > > > > IOPMP can only detect partially hit in an access. DMA device will split a > > large DMA transfer to small DMA transfers base on target and DMA transfer > > width, so partially hit error only happens when an access cross the > > boundary. > > But to ensure that an access is only within one entry is still important. > > For example, an entry may mean permission of a device memory region. We do > > not want to see one DMA transfer can access mutilple devices, although DMA > > have permissions from multiple entries. > > I was expecting a DMA request can be fulfilled successfully as long as the > DMA translations are valid for the whole range of the request, even if the > requested range may include two separate translated targets or more, each > point to different places (either RAM, or other devicie's MMIO regions). > > AFAIK currently QEMU memory model will automatically split that large > request into two or more smaller requests, and fulfill them separately by > two/more IOMMU translations, with its memory access dispatched to the > specific memory regions. > > The example you provided doesn't seem to be RISCV specific. Do you mean it > is a generic requirement from PCI/PCIe POV, or is it only a restriction of > IOPMP? If it's a valid PCI restriction, does it mean that all the rest > IOMMU implementations in QEMU currently are broken? > > [copy Michael and Igor] > > Thanks, > > -- > Peter Xu
-- Peter Xu
