I have noticed that the branches have some problem on the sparc target
in very rare conditions. This happens when a store double instruction
(std) is used in the delay slot, as in the following test:
tst %g0
bne 9b5d8
std %o2, [ %o1 ]
Inserting a nop between bne and std "fixes" the problem.
tst %g0 sets the zero flag, so that the branch should never be taked. It
happens however that it is sometimes taken. This seems to be due to the
fact that T2 holds the result of the condition, and std replace T2 with
another value. flush_T2() is called before altering T2, but it does not
seems to work.
I am currently stuck at that point, I hope somebody who has better
understanding of the branch code on Sparc could fix that.
Nice analysis, thanks. Flush_T2 is probably a misnomer. One solution could
be adding a new field to CPU structure for std's (and stda's) use, so that
T2 does not need to be used.
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