On Wed, Mar 21, 2007 at 09:34:46PM +0100, Aurelien Jarno wrote:
> Blue Swirl a écrit :
> >>From my tests, it seems that std in a delayed branch slot occurs a
> >> hundred of time during a boot, so not a lot. Adding a new field to the
> >> CPU structure would probably decrease the performances (except on
> >> hosts with a lot of registers). Therefore I am proposing something like
> >> that (currently for std only):
> >
> > Can you test if this works instead?
> >
>
> The first hunk works well, and is indeed better than my patch. The
> second hunk applies, but does not compile.
>
The patch below (that includes the first hunk of your patch) also fixes
stda. There is probably a smarter way to do that for the second hunk,
but that imply more changes.
Index: target-sparc/translate.c
===================================================================
RCS file: /sources/qemu/qemu/target-sparc/translate.c,v
retrieving revision 1.34
diff -u -d -p -r1.34 translate.c
--- target-sparc/translate.c 23 Oct 2006 21:37:34 -0000 1.34
+++ target-sparc/translate.c 21 Mar 2007 21:23:18 -0000
@@ -2454,8 +2454,8 @@ static void disas_sparc_insn(DisasContex
gen_op_ldst(sth);
break;
case 0x7:
- flush_T2(dc);
- gen_movl_reg_T2(rd + 1);
+ gen_op_ldst(st);
+ gen_movl_reg_T1(rd + 1);
gen_op_ldst(std);
break;
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
@@ -2485,9 +2485,11 @@ static void disas_sparc_insn(DisasContex
if (!supervisor(dc))
goto priv_insn;
#endif
- flush_T2(dc);
- gen_movl_reg_T2(rd + 1);
- gen_op_stda(insn, 0, 8, 0);
+ gen_op_stda(insn, 0, 4, 0);
+ gen_op_movl_T1_im(4);
+ gen_op_add_T1_T0();
+ gen_movl_reg_T1(rd + 1);
+ gen_op_stda(insn, 0, 4, 0);
break;
#endif
#ifdef TARGET_SPARC64
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' [EMAIL PROTECTED] | [EMAIL PROTECTED]
`- people.debian.org/~aurel32 | www.aurel32.net
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