On Wed, Dec 10, 2014 at 01:40:42PM -0700, Davey Hutchison wrote: > Fix pll_1000 value for eth0. Traffic would not flow from the eth0 interface. > The new PLL enables delay, use ath79_setup_ar934x_eth_cfg to also enable > AR934X_ETH_CFG_RXD_DELAY. > > Signed-off-by: Davey Hutchison <dhutchi...@bluemesh.net> > > --- target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c > +++ target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c > @@ -199,6 +199,7 @@ > return; > > ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | > + AR934X_ETH_CFG_RXD_DELAY | > AR934X_ETH_CFG_SW_ONLY_MODE); > > ath79_register_mdio(0, 0x0); > @@ -209,6 +210,7 @@ > ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); > ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; > ath79_eth0_data.phy_mask = BIT(0); > + ath79_eth0_pll_data.pll_1000 = 0x3e000000; > > ath79_register_eth(0);
This needs to be in mach-rb2011.c as well. -- Chris Green _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
