On Monday 11 January 2010, Thomas Kindler wrote:
> Joseph Yiu suggested this code to cause a hard-fault:
>
> __asm(
> "movs r0, #1 \t\n" // unaligned ..
> "ldm r0, {r1-r2} \t\n" // .. load-multiple
> "bx lr \t\n"
> );
>
> (see http://www.st.com/mcu/forums-cat-6778-23.html)
Doesn't that presume escalation to a HardFault because
you didn't enable UsageFault in SHCSR, and the system
handler priority registers cooperate?
Not everyone uses that escalation logic. But if it
works in your test cases, great. :)
My own runtime code enables all faults, so that if I
override the default loop-to-self handler (by just
providing a non-weak symbol) it will always kick in.
I'll take a closer look at this; it's clearly a
generic issue with Cortex-M3. And I really think
that the un-requested mucking with fault handling
is a bug in OpenOCD.
- Dave
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