David Brownell wrote: > On Monday 11 January 2010, Thomas Kindler wrote: >> How could this be fixed or explained? > > There's some curious voodoo in the Cortex-M3 code > where it mucks with fault handling ... see in the > cortex_m3_endreset_event() routine where it sets > up to trap some faults automagically. REVISIT > comments mark at least two curiousities, also a > FIXME with respect to a more easily seen bug.
Thanks! That seems to be the problem. If I grep for DEMCR, it's written not only in endreset, but also some other places. > If that's part of the issue, you might be able to > work around it by updating DEMCR before shutting > down. "cortex_m3 vector_catch none" maybe. Well, it helps a bit. Adding "CoreDebug->DEMCR = 0;" to the start of my program does the same. I still need to do a system reset (but no power-cycle), before the processor executes hard faults again! .. strange. > Re needing a power cycle, it's a bit suggestive that > DHCR and DEMCR are not cleared by "normal" reset... Yes, it's also in the cortex_m3_r1p1 manual: "This register is not reset on a system reset. This register is reset by a power-on reset. Bits [19:16] are always cleared on a core reset. The debug monitor is enabled by software in the reset handler or later, or by the AHB-AP port." _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
