On Tue, Oct 27, 2009 at 6:56 PM, David Brownell <davi...@pacbell.net> wrote:
> On Tuesday 27 October 2009, Yegor Yefremov wrote:
>> In the data sheets for all lm3s811 revisions only version 1 is
>> described. What to do with the stuff? Can revision number be made
>> "don't care" or for info purpose only, if it really has no impact on
>> the function?
>
> You can pass multiple "-expected-id NNNNNNNN" values
> in your upcoming "stellaris.cfg" file. Up to eight,
> if I recall right...
>
> Make sure you comment which TAP id corresponds to
> which CM3 and Stellaris part revision, and that you
> can still override one of them easily when a new
> CM3 revision starts to get deployed.
>
> We don't currently have a way to make revision be a
> "don't care". In *this* case it seems not to matter;
> integration details matter more. (Like that issue
> where SRST clobbers some debug state on earlier LM3S
> parts, despite ARM docs saying otherwise.)
>
> - Dave
Dave,
I've added the CPUTAPID for lm3s811. I've named the file luminary.cfg
as in interfaces. Could you review the patch? And one more question:
how can I override -work-area-size from my custom openocd.cfg?
Regards,
Yegor
Index: openocd/tcl/target/luminary.cfg
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ openocd/tcl/target/luminary.cfg 2009-11-02 12:46:04.000000000 +0100
@@ -0,0 +1,41 @@
+# TI/Luminary Stellaris lm3sxxxx
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME lm3sxxxx
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x3ba00477
+}
+
+# jtag speed
+jtag_khz 500
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#LM3Sxxxx Evaluation Board has only srst
+reset_config srst_only
+
+#jtag scan chain
+# CPU TAP ID 0x2ba00477 for lm3s811 Rev C2 added
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf
-expected-id 0x2ba00477 -expected-id $_CPUTAPID
+
+# the luminary variant causes a software reset rather than asserting SRST
+# this stops the debug registers from being cleared
+# this will be fixed in later revisions of silicon
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
-variant lm3s
+
+# 8k working area at base of ram, not backed up
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
+
+#flash configuration
+flash bank stellaris 0 0 0 0 $_TARGETNAME
+
+
+
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