gen6 does not support multiple miplevels with stencil. Therefore we
need to layout it's miptree with no LOD0 spacing between the slices of
each miplevel.
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
---
src/mesa/drivers/dri/i965/intel_fbo.c | 3 ++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 31 +++++++++++++++++---------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 6 +++--
src/mesa/drivers/dri/i965/intel_tex.c | 3 ++-
src/mesa/drivers/dri/i965/intel_tex_image.c | 3 ++-
src/mesa/drivers/dri/i965/intel_tex_subimage.c | 3 ++-
src/mesa/drivers/dri/i965/intel_tex_validate.c | 3 ++-
7 files changed, 35 insertions(+), 17 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
b/src/mesa/drivers/dri/i965/intel_fbo.c
index 22f707f..87abbf6 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -980,7 +980,8 @@ intel_renderbuffer_move_to_temp(struct brw_context *brw,
width, height, depth,
true,
irb->mt->num_samples,
- INTEL_MIPTREE_TILING_ANY);
+ INTEL_MIPTREE_TILING_ANY,
+ false);
if (brw_is_hiz_depth_format(brw, new_mt->format)) {
intel_miptree_alloc_hiz(brw, new_mt);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index b7d86a3..2d4224c 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -242,7 +242,8 @@ intel_miptree_create_layout(struct brw_context *brw,
GLuint height0,
GLuint depth0,
bool for_bo,
- GLuint num_samples)
+ GLuint num_samples,
+ bool force_array_spacing)
{
struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1);
if (!mt)
@@ -376,7 +377,8 @@ intel_miptree_create_layout(struct brw_context *brw,
mt->logical_depth0,
true,
num_samples,
- INTEL_MIPTREE_TILING_ANY);
+ INTEL_MIPTREE_TILING_ANY,
+ false);
if (!mt->stencil_mt) {
intel_miptree_release(&mt);
return NULL;
@@ -394,6 +396,9 @@ intel_miptree_create_layout(struct brw_context *brw,
}
}
+ if (force_array_spacing)
+ mt->array_spacing_lod0 = true;
+
brw_miptree_layout(brw, mt);
return mt;
@@ -548,7 +553,8 @@ intel_miptree_create(struct brw_context *brw,
GLuint depth0,
bool expect_accelerated_upload,
GLuint num_samples,
- enum intel_miptree_tiling_mode requested_tiling)
+ enum intel_miptree_tiling_mode requested_tiling,
+ bool force_array_spacing)
{
struct intel_mipmap_tree *mt;
mesa_format tex_format = format;
@@ -562,7 +568,8 @@ intel_miptree_create(struct brw_context *brw,
mt = intel_miptree_create_layout(brw, target, format,
first_level, last_level, width0,
height0, depth0,
- false, num_samples);
+ false, num_samples,
+ force_array_spacing);
/*
* pitch == 0 || height == 0 indicates the null texture
*/
@@ -673,7 +680,7 @@ intel_miptree_create_for_bo(struct brw_context *brw,
mt = intel_miptree_create_layout(brw, GL_TEXTURE_2D, format,
0, 0,
width, height, 1,
- true, 0 /* num_samples */);
+ true, 0, false);
if (!mt) {
free(mt);
return mt;
@@ -782,7 +789,7 @@ intel_miptree_create_for_renderbuffer(struct brw_context
*brw,
mt = intel_miptree_create(brw, target, format, 0, 0,
width, height, depth, true, num_samples,
- INTEL_MIPTREE_TILING_ANY);
+ INTEL_MIPTREE_TILING_ANY, false);
if (!mt)
goto fail;
@@ -1283,7 +1290,8 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
mt->logical_depth0,
true,
0 /* num_samples */,
- INTEL_MIPTREE_TILING_Y);
+ INTEL_MIPTREE_TILING_Y,
+ false);
/* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
*
@@ -1340,7 +1348,8 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
mt->logical_depth0,
true,
0 /* num_samples */,
- INTEL_MIPTREE_TILING_Y);
+ INTEL_MIPTREE_TILING_Y,
+ false);
return mt->mcs_mt;
}
@@ -1394,7 +1403,8 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
mt->logical_depth0,
true,
mt->num_samples,
- INTEL_MIPTREE_TILING_ANY);
+ INTEL_MIPTREE_TILING_ANY,
+ false);
if (!mt->hiz_mt)
return false;
@@ -1775,7 +1785,8 @@ intel_miptree_map_blit(struct brw_context *brw,
0, 0,
map->w, map->h, 1,
false, 0,
- INTEL_MIPTREE_TILING_NONE);
+ INTEL_MIPTREE_TILING_NONE,
+ false);
if (!map->mt) {
fprintf(stderr, "Failed to allocate blit temporary\n");
goto fail;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 6a91884..b1b3d77 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -454,7 +454,8 @@ struct intel_mipmap_tree *intel_miptree_create(struct
brw_context *brw,
GLuint depth0,
bool expect_accelerated_upload,
GLuint num_samples,
- enum intel_miptree_tiling_mode);
+ enum intel_miptree_tiling_mode,
+ bool force_array_spacing);
struct intel_mipmap_tree *
intel_miptree_create_layout(struct brw_context *brw,
@@ -466,7 +467,8 @@ intel_miptree_create_layout(struct brw_context *brw,
GLuint height0,
GLuint depth0,
bool for_bo,
- GLuint num_samples);
+ GLuint num_samples,
+ bool force_array_spacing);
struct intel_mipmap_tree *
intel_miptree_create_for_bo(struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/intel_tex.c
b/src/mesa/drivers/dri/i965/intel_tex.c
index f18ca45..411d860 100644
--- a/src/mesa/drivers/dri/i965/intel_tex.c
+++ b/src/mesa/drivers/dri/i965/intel_tex.c
@@ -145,7 +145,8 @@ intel_alloc_texture_storage(struct gl_context *ctx,
width, height, depth,
false, /* expect_accelerated */
num_samples,
- INTEL_MIPTREE_TILING_ANY);
+ INTEL_MIPTREE_TILING_ANY,
+ false);
}
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c
b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 4eb024f..9f8173b 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -79,7 +79,8 @@ intel_miptree_create_for_teximage(struct brw_context *brw,
depth,
expect_accelerated_upload,
intelImage->base.Base.NumSamples,
- INTEL_MIPTREE_TILING_ANY);
+ INTEL_MIPTREE_TILING_ANY,
+ false);
}
/* XXX: Do this for TexSubImage also:
diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
index 5d79750..70bd5e0 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
@@ -129,7 +129,8 @@ intel_blit_texsubimage(struct gl_context * ctx,
intel_miptree_create(brw, GL_TEXTURE_2D, texImage->TexFormat,
0, 0,
width, height, 1,
- false, 0, INTEL_MIPTREE_TILING_NONE);
+ false, 0, INTEL_MIPTREE_TILING_NONE,
+ false);
if (!temp_mt)
goto err;
diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c
b/src/mesa/drivers/dri/i965/intel_tex_validate.c
index 07f3174..7dee0b2 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c
@@ -142,7 +142,8 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint
unit)
depth,
true,
0 /* num_samples */,
- INTEL_MIPTREE_TILING_ANY);
+ INTEL_MIPTREE_TILING_ANY,
+ false);
if (!intelObj->mt)
return false;
}
--
2.0.0.rc4
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