(a23cfb8 for gen6)
In layered rendering this will be 0. Otherwise it will be the
selected slice.
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
---
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 3 +++
src/mesa/drivers/dri/i965/gen6_depth_state.c | 10 ++++++++++
2 files changed, 13 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 3f6b929..5a55676 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -794,6 +794,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context
*brw,
uint32_t tile_mask_x, tile_mask_y;
uint32_t surftype;
unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
+ unsigned int min_array_element;
GLenum gl_target = params->depth.mt->target;
unsigned int lod;
@@ -819,6 +820,8 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context
*brw,
NULL,
&tile_mask_x, &tile_mask_y);
+ min_array_element = params->depth.layer;
+
lod = params->depth.level - params->depth.mt->first_level;
/* 3DSTATE_DEPTH_BUFFER */
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c
b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index 0fd8882..cacc6ee 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -136,6 +136,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
struct gl_framebuffer *fb = ctx->DrawBuffer;
uint32_t surftype;
unsigned int depth = 1;
+ unsigned int min_array_element;
GLenum gl_target = GL_TEXTURE_2D;
unsigned int lod;
const struct intel_renderbuffer *irb = NULL;
@@ -188,6 +189,15 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
break;
}
+ if (fb->MaxNumLayers > 0 || !irb) {
+ min_array_element = 0;
+ } else if (irb->mt->num_samples > 1) {
+ /* Convert physical layer to logical layer. */
+ min_array_element = irb->mt_layer / irb->mt->num_samples;
+ } else {
+ min_array_element = irb->mt_layer;
+ }
+
lod = irb ? irb->mt_level - irb->mt->first_level : 0;
unsigned int len;
--
2.0.0.rc4
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