gen6 stencil only supports LOD0 for stencil, forcing us to use an
array_spacing_lod0 type of miptree layout.
We use a combination of array_spacing_lod0 and a regular miptree in
that all slices of a particular LOD are combined without spacing for
additional LODs. This allows the surface to be set up like the
hardware expects, and also tries to minimize the overall texture size.
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 2d4224c..aff00b0 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -367,6 +367,7 @@ intel_miptree_create_layout(struct brw_context *brw,
_mesa_get_format_base_format(format) == GL_DEPTH_STENCIL &&
(brw->must_use_separate_stencil ||
(brw->has_separate_stencil && brw_is_hiz_depth_format(brw, format)))) {
+ bool separate_lods = brw->gen == 6;
mt->stencil_mt = intel_miptree_create(brw,
mt->target,
MESA_FORMAT_S_UINT8,
@@ -378,7 +379,7 @@ intel_miptree_create_layout(struct brw_context *brw,
true,
num_samples,
INTEL_MIPTREE_TILING_ANY,
- false);
+ separate_lods);
if (!mt->stencil_mt) {
intel_miptree_release(&mt);
return NULL;
@@ -1393,6 +1394,7 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
assert(mt->hiz_mt == NULL);
+ bool separate_lods = brw->gen == 6;
mt->hiz_mt = intel_miptree_create(brw,
mt->target,
mt->format,
@@ -1404,7 +1406,7 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
true,
mt->num_samples,
INTEL_MIPTREE_TILING_ANY,
- false);
+ separate_lods);
if (!mt->hiz_mt)
return false;
--
2.0.0.rc4
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