Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 8a0912d..9293229 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -318,9 +318,19 @@ void
brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt)
{
bool multisampled = mt->num_samples > 1;
- mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt->format);
- mt->align_h =
- intel_vertical_texture_alignment_unit(brw, mt->format, multisampled);
+
+ if (brw->gen == 6 && mt->array_spacing_lod0) {
+ /* On gen6, we use array_spacing_lod0 for stencil/hiz because the
+ hardware doesn't support multiple mip levels on stencil. Stencil uses
+ W tiling, so we force W tiling alignment when array_spacing_lod0 is
+ requested. */
+ mt->align_w = 64;
+ mt->align_h = 64;
+ } else {
+ mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt->format);
+ mt->align_h =
+ intel_vertical_texture_alignment_unit(brw, mt->format, multisampled);
+ }
switch (mt->target) {
case GL_TEXTURE_CUBE_MAP:
--
2.0.0.rc4
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