This will be used in 3DSTATE_DEPTH_BUFFER in a later patch.
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
---
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 3 +++
src/mesa/drivers/dri/i965/gen7_misc_state.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 1ec05ad..7df78f6 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -660,6 +660,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context
*brw,
uint32_t surftype;
int depth = MAX2(params->depth.mt->logical_depth0, 1);
GLenum gl_target = params->depth.mt->target;
+ int lod;
brw_get_depthstencil_tile_masks(params->depth.mt,
params->depth.level,
@@ -677,6 +678,8 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context
*brw,
break;
}
+ lod = params->depth.level - params->depth.mt->first_level;
+
/* 3DSTATE_DEPTH_BUFFER */
{
uint32_t tile_x = draw_x & tile_mask_x;
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 798da41..14257cc 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -45,6 +45,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
uint32_t surftype;
int depth = 1;
GLenum gl_target = GL_TEXTURE_2D;
+ int lod;
const struct intel_renderbuffer *irb = NULL;
const struct gl_renderbuffer *rb = NULL;
@@ -72,6 +73,8 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
break;
}
+ lod = irb ? irb->mt_level - irb->mt->first_level : 0;
+
/* _NEW_DEPTH, _NEW_STENCIL, _NEW_BUFFERS */
BEGIN_BATCH(7);
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
--
1.7.10.4
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