git://people.freedesktop.org/~jljusten/mesa ivb-full-depth-buffer-v1
This series converts DEPTH_BUFFER to use the LOD and
minimum array element fields and always points the
depth, hiz and stencil buffers at the top of the
miptree surface.
This should allows us to support layered rendering,
although testing of this is not completed. Layered
rendering will be required for GL 3.2 / GLSL 1.50
support, but it can also be exposed via the
GL_AMD_vertex_shader_layer extension.
Testing on this series (IVB and HSW):
* Piglit: Fixes array-depth-roundtrip
* Basic visual inspection of Unigine Tropics
Jordan Justen (12):
i965: init global state first in
brw_workaround_depthstencil_alignment
gen7 depth surface: calculate more specific surface type
gen7 depth surface: calculate depth (array size) for depth surface
gen7 depth surface: calculate LOD being rendered to
gen7 depth surface: determine if layered rendering is being used
gen7 depth surface: calculate minimum array element being rendered
gen7 blorp depth: calculate base surface width/height
hsw hiz: Add new size restrictions for miplevels > 0
gen7 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surface
hsw hiz: Remove x/y offset restriction for hiz
i965 gen7: don't set FORCE_ZERO_RTAINDEX in clip state
intel: enable GL_AMD_vertex_shader_layer extension for gen7+
src/mesa/drivers/dri/i965/brw_misc_state.c | 25 +++++--
src/mesa/drivers/dri/i965/brw_tex_layout.c | 10 +--
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 93 ++++++++++++-------------
src/mesa/drivers/dri/i965/gen7_clip_state.c | 3 +-
src/mesa/drivers/dri/i965/gen7_misc_state.c | 87 ++++++++++++++++++++---
src/mesa/drivers/dri/i965/intel_extensions.c | 4 ++
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 30 +++-----
7 files changed, 157 insertions(+), 95 deletions(-)
--
1.7.10.4
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