From: Francisco Jerez <curroje...@riseup.net>
The hardware's control flow logic is 16-wide so we're out of luck
here.
Change-Id: I788fd3d2cc74b53ce3304e250f709b82f95624d8
---
src/intel/compiler/brw_fs_nir.cpp | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index 3b8cfda..d3cd8f7 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -384,6 +384,10 @@ fs_visitor::nir_emit_if(nir_if *if_stmt)
nir_emit_cf_list(&if_stmt->else_list);
bld.emit(BRW_OPCODE_ENDIF);
+
+ if (devinfo->gen < 7)
+ limit_dispatch_width(16, "Non-uniform control flow unsupported "
+ "in SIMD32 mode.");
}
void
@@ -394,6 +398,10 @@ fs_visitor::nir_emit_loop(nir_loop *loop)
nir_emit_cf_list(&loop->body);
bld.emit(BRW_OPCODE_WHILE);
+
+ if (devinfo->gen < 7)
+ limit_dispatch_width(16, "Non-uniform control flow unsupported "
+ "in SIMD32 mode.");
}
void
--
2.7.4
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