From: Kevin Rogovin <kevin.rogo...@intel.com>
Change-Id: Ie75461470039c0fc04fbd5a4a2f65c7c6d623c21
Signed-off-by: valtteri rantala <valtteri.rant...@intel.com>
---
src/intel/compiler/brw_eu_defines.h | 1 -
src/intel/compiler/brw_fs.cpp | 27 +++++++++++++++++----------
src/intel/compiler/brw_fs.h | 2 +-
src/intel/compiler/brw_fs_cse.cpp | 1 -
src/intel/compiler/brw_fs_generator.cpp | 3 ---
src/intel/compiler/brw_fs_nir.cpp | 16 +++++++---------
src/intel/compiler/brw_fs_visitor.cpp | 10 ++++------
src/intel/compiler/brw_shader.cpp | 6 +-----
8 files changed, 30 insertions(+), 36 deletions(-)
diff --git a/src/intel/compiler/brw_eu_defines.h
b/src/intel/compiler/brw_eu_defines.h
index 332d627..36519af 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -499,7 +499,6 @@ enum opcode {
*/
FS_OPCODE_DDY_COARSE,
FS_OPCODE_DDY_FINE,
- FS_OPCODE_CINTERP,
FS_OPCODE_LINTERP,
FS_OPCODE_PIXEL_X,
FS_OPCODE_PIXEL_Y,
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index b21996c..fc41604 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -1079,8 +1079,8 @@ fs_visitor::emit_fragcoord_interpolation(fs_reg wpos)
bld.MOV(wpos, fs_reg(brw_vec8_grf(payload.source_depth_reg, 0)));
} else {
bld.emit(FS_OPCODE_LINTERP, wpos,
- this->delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL],
- interp_reg(VARYING_SLOT_POS, 2));
+ this->delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL],
+ component(interp_reg(VARYING_SLOT_POS, 2), 0));
}
wpos = offset(wpos, bld, 1);
@@ -1609,14 +1609,21 @@ fs_visitor::assign_urb_setup()
* setup regs, now that the location of the constants has been chosen.
*/
foreach_block_and_inst(block, fs_inst, inst, cfg) {
- if (inst->opcode == FS_OPCODE_LINTERP) {
- assert(inst->src[1].file == FIXED_GRF);
- inst->src[1].nr += urb_start;
- }
-
- if (inst->opcode == FS_OPCODE_CINTERP) {
- assert(inst->src[0].file == FIXED_GRF);
- inst->src[0].nr += urb_start;
+ for (int i = 0; i < inst->sources; i++) {
+ if (inst->src[i].file == ATTR) {
+ const unsigned nr =
+ urb_start + inst->src[i].nr + inst->src[i].offset / REG_SIZE;
+ const unsigned width = inst->src[i].stride == 0 ?
+ 1 : MIN2(inst->exec_size, 8);
+ struct brw_reg reg = stride(
+ byte_offset(retype(brw_vec8_grf(nr, 0), inst->src[i].type),
+ inst->src[i].offset % REG_SIZE),
+ width * inst->src[i].stride,
+ width, inst->src[i].stride);
+ reg.abs = inst->src[i].abs;
+ reg.negate = inst->src[i].negate;
+ inst->src[i] = reg;
+ }
}
}
diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index e384db8..faf5156 100644
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -276,7 +276,7 @@ public:
fs_reg get_timestamp(const brw::fs_builder &bld);
- struct brw_reg interp_reg(int location, int channel);
+ fs_reg interp_reg(int location, int channel);
int implied_mrf_writes(fs_inst *inst) const;
diff --git a/src/intel/compiler/brw_fs_cse.cpp
b/src/intel/compiler/brw_fs_cse.cpp
index 48220ef..6859733 100644
--- a/src/intel/compiler/brw_fs_cse.cpp
+++ b/src/intel/compiler/brw_fs_cse.cpp
@@ -75,7 +75,6 @@ is_expression(const fs_visitor *v, const fs_inst *const inst)
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
- case FS_OPCODE_CINTERP:
case FS_OPCODE_LINTERP:
case SHADER_OPCODE_FIND_LIVE_CHANNEL:
case SHADER_OPCODE_BROADCAST:
diff --git a/src/intel/compiler/brw_fs_generator.cpp
b/src/intel/compiler/brw_fs_generator.cpp
index 6d5306a..89f88d3 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -2105,9 +2105,6 @@ fs_generator::generate_code(const cfg_t *cfg, int
dispatch_width)
BRW_MATH_PRECISION_FULL);
}
break;
- case FS_OPCODE_CINTERP:
- brw_MOV(p, dst, src[0]);
- break;
case FS_OPCODE_LINTERP:
multiple_instructions_emitted = generate_linterp(inst, dst, src);
break;
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index 1705cd6..3b8cfda 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -3326,15 +3326,15 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder &bld,
case nir_intrinsic_load_input: {
/* load_input is only used for flat inputs */
unsigned base = nir_intrinsic_base(instr);
- unsigned component = nir_intrinsic_component(instr);
+ unsigned comp = nir_intrinsic_component(instr);
unsigned num_components = instr->num_components;
enum brw_reg_type type = dest.type;
/* Special case fields in the VUE header */
if (base == VARYING_SLOT_LAYER)
- component = 1;
+ comp = 1;
else if (base == VARYING_SLOT_VIEWPORT)
- component = 2;
+ comp = 2;
if (nir_dest_bit_size(instr->dest) == 64) {
/* const_index is in 32-bit type size units that could not be aligned
@@ -3346,10 +3346,8 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder &bld,
}
for (unsigned int i = 0; i < num_components; i++) {
- struct brw_reg interp = interp_reg(base, component + i);
- interp = suboffset(interp, 3);
- bld.emit(FS_OPCODE_CINTERP, offset(retype(dest, type), bld, i),
- retype(fs_reg(interp), type));
+ bld.MOV(offset(retype(dest, type), bld, i),
+ retype(component(interp_reg(base, comp + i), 3), type));
}
if (nir_dest_bit_size(instr->dest) == 64) {
@@ -3522,8 +3520,8 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder &bld,
for (unsigned int i = 0; i < instr->num_components; i++) {
fs_reg interp =
- fs_reg(interp_reg(nir_intrinsic_base(instr),
- nir_intrinsic_component(instr) + i));
+ component(interp_reg(nir_intrinsic_base(instr),
+ nir_intrinsic_component(instr) + i), 0);
interp.type = BRW_REGISTER_TYPE_F;
dest.type = BRW_REGISTER_TYPE_F;
diff --git a/src/intel/compiler/brw_fs_visitor.cpp
b/src/intel/compiler/brw_fs_visitor.cpp
index 7a5f645..2805ec2 100644
--- a/src/intel/compiler/brw_fs_visitor.cpp
+++ b/src/intel/compiler/brw_fs_visitor.cpp
@@ -135,17 +135,15 @@ fs_visitor::emit_dummy_fs()
* data. It will get adjusted to be a real location before
* generate_code() time.
*/
-struct brw_reg
+fs_reg
fs_visitor::interp_reg(int location, int channel)
{
assert(stage == MESA_SHADER_FRAGMENT);
struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
- int regnr = prog_data->urb_setup[location] * 2 + channel / 2;
- int stride = (channel & 1) * 4;
-
+ int regnr = prog_data->urb_setup[location] * 16 + channel * 4;
assert(prog_data->urb_setup[location] != -1);
- return brw_vec1_grf(regnr, stride);
+ return horiz_offset(fs_reg(ATTR, 0, BRW_REGISTER_TYPE_F), regnr);
}
/** Emits the interpolation for the varying inputs. */
@@ -192,7 +190,7 @@ fs_visitor::emit_interpolation_setup_gen4()
*/
this->wpos_w = vgrf(glsl_type::float_type);
abld.emit(FS_OPCODE_LINTERP, wpos_w, delta_xy,
- interp_reg(VARYING_SLOT_POS, 3));
+ component(interp_reg(VARYING_SLOT_POS, 3), 0));
/* Compute the pixel 1/W value from wpos.w. */
this->pixel_w = vgrf(glsl_type::float_type);
abld.emit(SHADER_OPCODE_RCP, this->pixel_w, wpos_w);
diff --git a/src/intel/compiler/brw_shader.cpp
b/src/intel/compiler/brw_shader.cpp
index 9cdf9fc..f0e1443 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -378,8 +378,6 @@ brw_instruction_name(const struct gen_device_info *devinfo,
enum opcode op)
case FS_OPCODE_DDY_FINE:
return "ddy_fine";
- case FS_OPCODE_CINTERP:
- return "cinterp";
case FS_OPCODE_LINTERP:
return "linterp";
@@ -954,7 +952,6 @@ backend_instruction::can_do_cmod() const
case BRW_OPCODE_SHR:
case BRW_OPCODE_SUBB:
case BRW_OPCODE_XOR:
- case FS_OPCODE_CINTERP:
case FS_OPCODE_LINTERP:
return true;
default:
@@ -981,8 +978,7 @@ backend_instruction::writes_accumulator_implicitly(const
struct gen_device_info
return writes_accumulator ||
(devinfo->gen < 6 &&
((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
- (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
- opcode != FS_OPCODE_CINTERP)));
+ (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP)));
}
bool
--
2.7.4
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
