On 20.03.2017 23:43, Marek Olšák wrote:
From: Marek Olšák <marek.ol...@amd.com>
Both GFX6 and GFX9 fields are printed next to each other in parsed IBs.
The Python script parses both headers like one stream and tries to merge
all definitions.
---
src/amd/Makefile.common.am | 4 +--
src/amd/common/ac_debug.c | 1 +
src/amd/common/sid_tables.py | 54 ++++++++++++++++++++++-----------
src/gallium/drivers/radeonsi/si_debug.c | 1 +
4 files changed, 41 insertions(+), 19 deletions(-)
diff --git a/src/amd/Makefile.common.am b/src/amd/Makefile.common.am
index e492fbc..595876f 100644
--- a/src/amd/Makefile.common.am
+++ b/src/amd/Makefile.common.am
@@ -58,15 +58,15 @@ common_libamd_common_la_SOURCES = \
$(AMD_DEBUG_FILES) \
$(AMD_GENERATED_FILES)
# nir_to_llvm requires LLVM 3.9, which is only required as a minimum when
# radv is built.
if HAVE_RADEON_VULKAN
common_libamd_common_la_SOURCES += $(AMD_NIR_FILES)
endif
endif
-common/sid_tables.h: $(srcdir)/common/sid_tables.py $(srcdir)/common/sid.h
+common/sid_tables.h: $(srcdir)/common/sid_tables.py $(srcdir)/common/sid.h
$(srcdir)/common/gfx9d.h
$(AM_V_at)$(MKDIR_P) $(@D)
- $(AM_V_GEN) $(PYTHON2) $(srcdir)/common/sid_tables.py
$(srcdir)/common/sid.h > $@
+ $(AM_V_GEN) $(PYTHON2) $(srcdir)/common/sid_tables.py
$(srcdir)/common/sid.h $(srcdir)/common/gfx9d.h > $@
BUILT_SOURCES = $(AMD_GENERATED_FILES)
diff --git a/src/amd/common/ac_debug.c b/src/amd/common/ac_debug.c
index 989dfda..9d051f9 100644
--- a/src/amd/common/ac_debug.c
+++ b/src/amd/common/ac_debug.c
@@ -20,20 +20,21 @@
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* Authors:
* Marek Olšák <mar...@gmail.com>
*/
#include "ac_debug.h"
#include "sid.h"
+#include "gfx9d.h"
#include "sid_tables.h"
#include "util/u_math.h"
#include "util/u_memory.h"
/* Parsed IBs are difficult to read without colors. Use "less -R file" to
* read them, or use "aha -b -f file" to convert them to html.
*/
#define COLOR_RESET "\033[0m"
#define COLOR_RED "\033[31m"
#define COLOR_GREEN "\033[1;32m"
diff --git a/src/amd/common/sid_tables.py b/src/amd/common/sid_tables.py
index df2d7ec..429766e 100644
--- a/src/amd/common/sid_tables.py
+++ b/src/amd/common/sid_tables.py
@@ -138,43 +138,66 @@ class Reg:
self.r_name = r_name
self.name = strip_prefix(r_name)
self.fields = []
self.own_fields = True
def strip_prefix(s):
'''Strip prefix in the form ._.*_, e.g. R_001234_'''
return s[s[2:].find('_')+3:]
-
-def parse(filename):
+def parse(filename, regs, packets):
stream = open(filename)
- regs = []
- packets = []
for line in stream:
if not line.startswith('#define '):
continue
line = line[8:].strip()
if line.startswith('R_'):
- reg = Reg(line.split()[0])
- regs.append(reg)
+ name = line.split()[0]
+
+ reg = None
+ for it in regs:
+ if it.r_name == name:
+ reg = it
+ break
+
+ if reg == None:
+ reg = Reg(name)
+ regs.append(reg)
Python has the pretty cool for-else syntax which you can use here instead:
(skip the reg = None line)
for it in regs:
if it.r_name == name:
reg = it
break
else:
reg = Reg(name)
regs.append(reg)
The else-part runs precisely when the for-loop finishes without hitting
the break, so it's a nice idiomatic pattern for this kind of
find-or-create code.
There is one more instance of this below.
Either way, patch is
Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
elif line.startswith('S_'):
- field = Field(reg, line[:line.find('(')])
- reg.fields.append(field)
+ name = line[:line.find('(')]
+
+ field = None
+ for it in reg.fields:
+ if it.s_name == name:
+ field = it
+ break
+
+ if field == None:
+ field = Field(reg, name)
+ reg.fields.append(field)
elif line.startswith('V_'):
split = line.split()
- field.values.append((split[0], int(split[1], 0)))
+ name = split[0]
+ value = int(split[1], 0)
+
+ for (n,v) in field.values:
+ if n == name:
+ if v != value:
+ sys.exit('Value mismatch: name = ' + name)
+
+ field.values.append((name, value))
elif line.startswith('PKT3_') and line.find('0x') != -1 and
line.find('(') == -1:
packets.append(line.split()[0])
# Copy fields to indexed registers which have their fields only defined
# at register index 0.
# For example, copy fields from CB_COLOR0_INFO to CB_COLORn_INFO, n > 0.
match_number = re.compile('[0-9]+')
reg_dict = dict()
@@ -185,26 +208,22 @@ def parse(filename):
# Assign fields
for reg in regs:
if not len(reg.fields):
reg0 = reg_dict.get(match_number.sub('0', reg.name))
if reg0 != None:
reg.fields = reg0.fields
reg.fields_owner = reg0
reg.own_fields = False
- return (regs, packets)
-
-def write_tables(tables):
- regs = tables[0]
- packets = tables[1]
+def write_tables(regs, packets):
strings = StringTable()
strings_offsets = IntTable("int")
print '/* This file is autogenerated by sid_tables.py from sid.h. Do not
edit directly. */'
print
print CopyRight.strip()
print '''
#ifndef SID_TABLES_H
#define SID_TABLES_H
@@ -275,20 +294,21 @@ struct si_packet3 {
print
strings_offsets.emit(sys.stdout, "sid_strings_offsets")
print
print '#endif'
def main():
- tables = []
+ regs = []
+ packets = []
for arg in sys.argv[1:]:
- tables.extend(parse(arg))
- write_tables(tables)
+ parse(arg, regs, packets)
+ write_tables(regs, packets)
if __name__ == '__main__':
main()
# kate: space-indent on; indent-width 4; replace-tabs on;
diff --git a/src/gallium/drivers/radeonsi/si_debug.c
b/src/gallium/drivers/radeonsi/si_debug.c
index 1092aa2..db310b7 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -19,20 +19,21 @@
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* Authors:
* Marek Olšák <mar...@gmail.com>
*/
#include "si_pipe.h"
#include "sid.h"
+#include "gfx9d.h"
#include "sid_tables.h"
#include "ddebug/dd_util.h"
#include "util/u_memory.h"
#include "ac_debug.h"
DEBUG_GET_ONCE_OPTION(replace_shaders, "RADEON_REPLACE_SHADERS", NULL)
static void si_dump_shader(struct si_screen *sscreen,
struct si_shader_ctx_state *state, FILE *f)
{
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