From: Xavi Zhang <xavi.zh...@amd.com>
---
src/amd/addrlib/r800/ciaddrlib.cpp | 35 +++++++++----------
src/amd/addrlib/r800/ciaddrlib.h | 6 ++--
src/amd/addrlib/r800/egbaddrlib.cpp | 70 ++++++++++++-------------------------
src/amd/addrlib/r800/egbaddrlib.h | 8 ++---
src/amd/addrlib/r800/siaddrlib.cpp | 23 +++++-------
src/amd/addrlib/r800/siaddrlib.h | 6 ++--
6 files changed, 56 insertions(+), 92 deletions(-)
diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp
b/src/amd/addrlib/r800/ciaddrlib.cpp
index 7272c49..cf08566 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -889,21 +889,21 @@ VOID CiLib::HwlOptimizeTileMode(
// Override 2D/3D macro tile mode to PRT_* tile mode if
// client driver requests this surface is equation compatible
if ((pInOut->flags.needEquation == TRUE) &&
(pInOut->numSamples <= 1) &&
(IsMacroTiled(tileMode) == TRUE) &&
(IsPrtTileMode(tileMode) == FALSE))
{
UINT_32 thickness = Thickness(tileMode);
- if (pInOut->maxBaseAlign < Block64K)
+ if ((pInOut->maxBaseAlign != 0) && (pInOut->maxBaseAlign < Block64K))
{
tileMode = (thickness == 1) ? ADDR_TM_1D_TILED_THIN1 :
ADDR_TM_1D_TILED_THICK;
}
else if (thickness == 1)
{
tileMode = ADDR_TM_PRT_TILED_THIN1;
}
else
{
static const UINT_32 PrtTileBytes = 0x10000;
@@ -1206,21 +1206,21 @@ VOID CiLib::HwlSetupTileInfo(
AddrTileType inTileType, ///< [in] Tile type
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [out] Output
) const
{
UINT_32 thickness = Thickness(tileMode);
ADDR_TILEINFO* pTileInfo = pTileInfoOut;
INT index = TileIndexInvalid;
INT macroModeIndex = TileIndexInvalid;
// Fail-safe code
- if (!IsLinear(tileMode))
+ if (IsLinear(tileMode) == FALSE)
{
// Thick tile modes must use thick micro tile mode but Bonaire does
not support due to
// old derived netlists (UBTS 404321)
if (thickness > 1)
{
if (m_settings.isBonaire)
{
inTileType = ADDR_NON_DISPLAYABLE;
}
else if ((m_allowNonDispThickModes == FALSE) ||
@@ -1818,23 +1818,20 @@ INT_32 CiLib::HwlComputeMacroModeIndex(
if (tileBytes < 64)
{
tileBytes = 64;
}
macroModeIndex = Log2(tileBytes / 64);
if (flags.prt || IsPrtTileMode(tileMode))
{
- // Unknown - assume it is 1/2 of table size
- const UINT_32 PrtMacroModeOffset = MacroTileTableSize / 2;
-
macroModeIndex += PrtMacroModeOffset;
*pTileInfo = m_macroTileTable[macroModeIndex];
}
else
{
*pTileInfo = m_macroTileTable[macroModeIndex];
}
pTileInfo->pipeConfig = m_tileTable[tileIndex].info.pipeConfig;
@@ -2020,39 +2017,41 @@ UINT_64 CiLib::HwlComputeMetadataNibbleAddress(
/**
****************************************************************************************************
* CiLib::HwlComputeSurfaceAlignmentsMacroTiled
*
* @brief
* Hardware layer function to compute alignment request for macro tile
mode
*
****************************************************************************************************
*/
VOID CiLib::HwlComputeSurfaceAlignmentsMacroTiled(
- AddrTileMode tileMode, ///< [in] tile mode
- UINT_32 bpp, ///< [in] bits per pixel
- ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
- UINT_32 mipLevel, ///< [in] mip level
- UINT_32 numSamples, ///< [in] number of samples
- ADDR_TILEINFO* pTileInfo, ///< [in,out] bank structure.
- UINT_32* pBaseAlign, ///< [out] base address alignment
in bytes
- UINT_32* pPitchAlign, ///< [out] pitch alignment in
pixels
- UINT_32* pHeightAlign, ///< [out] height alignment in
pixels
- UINT_32* pMacroTileWidth, ///< [out] macro tile width in
pixels
- UINT_32* pMacroTileHeight ///< [out] macro tile height in
pixels
+ AddrTileMode tileMode, ///< [in] tile mode
+ UINT_32 bpp, ///< [in] bits per
pixel
+ ADDR_SURFACE_FLAGS flags, ///< [in] surface
flags
+ UINT_32 mipLevel, ///< [in] mip level
+ UINT_32 numSamples, ///< [in] number of
samples
+ ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [in,out]
Surface output
) const
{
+ // This is to workaround a H/W limitation that DCC doesn't work when pipe
config is switched to
+ // P4. In theory, all asics that have such switching should be patched but
we now only know what
+ // to pad for Fiji.
if ((m_settings.isFiji == TRUE) &&
(flags.dccCompatible == TRUE) &&
+ (flags.prt == FALSE) &&
(mipLevel == 0) &&
- (tileMode == ADDR_TM_PRT_TILED_THIN1))
+ (tileMode == ADDR_TM_PRT_TILED_THIN1) &&
+ (pOut->dccUnsupport == TRUE))
{
- *pPitchAlign = PowTwoAlign(*pPitchAlign, 256);
+ pOut->pitchAlign = PowTwoAlign(pOut->pitchAlign, 256);
+ // In case the client still requests DCC usage.
+ pOut->dccUnsupport = FALSE;
}
}
/**
****************************************************************************************************
* CiLib::HwlPadDimensions
*
* @brief
* Helper function to pad dimensions
*
diff --git a/src/amd/addrlib/r800/ciaddrlib.h b/src/amd/addrlib/r800/ciaddrlib.h
index 7fa6b75..93b2853 100644
--- a/src/amd/addrlib/r800/ciaddrlib.h
+++ b/src/amd/addrlib/r800/ciaddrlib.h
@@ -170,23 +170,21 @@ protected:
virtual ADDR_E_RETURNCODE
HwlGetMaxAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const;
virtual VOID HwlPadDimensions(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 mipLevel,
UINT_32* pPitch, UINT_32 *PitchAlign, UINT_32 height, UINT_32
heightAlign) const;
virtual VOID HwlComputeSurfaceAlignmentsMacroTiled(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
- UINT_32 mipLevel, UINT_32 numSamples, ADDR_TILEINFO* pTileInfo,
- UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign,
- UINT_32* pMacroTileWidth, UINT_32* pMacroTileHeight) const;
+ UINT_32 mipLevel, UINT_32 numSamples,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
private:
VOID ReadGbTileMode(
UINT_32 regValue, TileConfig* pCfg) const;
VOID ReadGbMacroTileCfg(
UINT_32 regValue, ADDR_TILEINFO* pCfg) const;
BOOL_32 InitTileSettingTable(
const UINT_32 *pSetting, UINT_32 noOfEntries);
@@ -200,20 +198,22 @@ private:
UINT_64 metadataBaseByteAddress,
UINT_32 metadataBitSize,
UINT_32 elementBitSize,
UINT_32 blockByteSize,
UINT_32 pipeInterleaveBytes,
UINT_32 numOfPipes,
UINT_32 numOfBanks,
UINT_32 numOfSamplesPerSplit) const;
static const UINT_32 MacroTileTableSize = 16;
+ static const UINT_32 PrtMacroModeOffset = MacroTileTableSize / 2;
+
ADDR_TILEINFO m_macroTileTable[MacroTileTableSize];
UINT_32 m_noOfMacroEntries;
BOOL_32 m_allowNonDispThickModes;
CIChipSettings m_settings;
};
} // V1
} // Addr
diff --git a/src/amd/addrlib/r800/egbaddrlib.cpp
b/src/amd/addrlib/r800/egbaddrlib.cpp
index 2d1123a..7942d20 100644
--- a/src/amd/addrlib/r800/egbaddrlib.cpp
+++ b/src/amd/addrlib/r800/egbaddrlib.cpp
@@ -456,26 +456,21 @@ BOOL_32 EgBasedLib::ComputeSurfaceInfoMacroTiled(
//
// Compute the surface restrictions as base
// SanityCheckMacroTiled is called in ComputeSurfaceAlignmentsMacroTiled
//
valid = ComputeSurfaceAlignmentsMacroTiled(expTileMode,
pIn->bpp,
pIn->flags,
pIn->mipLevel,
numSamples,
- pOut->pTileInfo,
- &pOut->baseAlign,
- &pOut->pitchAlign,
- &pOut->heightAlign,
- &pOut->blockWidth,
- &pOut->blockHeight);
+ pOut);
if (valid)
{
//
// Compute the micro tile thickness.
//
microTileThickness = Thickness(expTileMode);
//
// Find the correct tiling mode for mip levels
@@ -514,26 +509,21 @@ BOOL_32 EgBasedLib::ComputeSurfaceInfoMacroTiled(
//
// Re-cal alignment
//
if (expTileMode != origTileMode) // Tile mode is changed but still
macro-tiled
{
valid = ComputeSurfaceAlignmentsMacroTiled(expTileMode,
pIn->bpp,
pIn->flags,
pIn->mipLevel,
numSamples,
- pOut->pTileInfo,
- &pOut->baseAlign,
- &pOut->pitchAlign,
- &pOut->heightAlign,
- &pOut->blockWidth,
- &pOut->blockHeight);
+ pOut);
}
//
// Do padding
//
PadDimensions(expTileMode,
pIn->bpp,
pIn->flags,
numSamples,
pOut->pTileInfo,
@@ -847,33 +837,30 @@ BOOL_32 EgBasedLib::HwlReduceBankWidthHeight(
*
* @brief
* Compute 2D tiled surface alignment, calculation results are returned
through
* output parameters.
*
* @return
* TRUE if no error occurs
****************************************************************************************************
*/
BOOL_32 EgBasedLib::ComputeSurfaceAlignmentsMacroTiled(
- AddrTileMode tileMode, ///< [in] tile mode
- UINT_32 bpp, ///< [in] bits per pixel
- ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
- UINT_32 mipLevel, ///< [in] mip level
- UINT_32 numSamples, ///< [in] number of samples
- ADDR_TILEINFO* pTileInfo, ///< [in,out] bank structure.
- UINT_32* pBaseAlign, ///< [out] base address alignment
in bytes
- UINT_32* pPitchAlign, ///< [out] pitch alignment in
pixels
- UINT_32* pHeightAlign, ///< [out] height alignment in
pixels
- UINT_32* pMacroTileWidth, ///< [out] macro tile width in
pixels
- UINT_32* pMacroTileHeight ///< [out] macro tile height in
pixels
+ AddrTileMode tileMode, ///< [in] tile mode
+ UINT_32 bpp, ///< [in] bits per
pixel
+ ADDR_SURFACE_FLAGS flags, ///< [in] surface
flags
+ UINT_32 mipLevel, ///< [in] mip level
+ UINT_32 numSamples, ///< [in] number of
samples
+ ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [in,out]
Surface output
) const
{
+ ADDR_TILEINFO* pTileInfo = pOut->pTileInfo;
+
BOOL_32 valid = SanityCheckMacroTiled(pTileInfo);
if (valid)
{
UINT_32 macroTileWidth;
UINT_32 macroTileHeight;
UINT_32 tileSize;
UINT_32 bankHeightAlign;
UINT_32 macroAspectAlign;
@@ -917,43 +904,41 @@ BOOL_32 EgBasedLib::ComputeSurfaceAlignmentsMacroTiled(
bankHeightAlign,
pipes,
pTileInfo);
//
// The required granularity for pitch is the macro tile width.
//
macroTileWidth = MicroTileWidth * pTileInfo->bankWidth * pipes *
pTileInfo->macroAspectRatio;
- *pPitchAlign = macroTileWidth;
- *pMacroTileWidth = macroTileWidth;
+ pOut->pitchAlign = macroTileWidth;
+ pOut->blockWidth = macroTileWidth;
- AdjustPitchAlignment(flags, pPitchAlign);
+ AdjustPitchAlignment(flags, &pOut->pitchAlign);
//
// The required granularity for height is the macro tile height.
//
macroTileHeight = MicroTileHeight * pTileInfo->bankHeight *
pTileInfo->banks /
pTileInfo->macroAspectRatio;
- *pHeightAlign = macroTileHeight;
- *pMacroTileHeight = macroTileHeight;
+ pOut->heightAlign = macroTileHeight;
+ pOut->blockHeight = macroTileHeight;
//
// Compute base alignment
//
- *pBaseAlign = pipes *
- pTileInfo->bankWidth * pTileInfo->banks * pTileInfo->bankHeight *
tileSize;
+ pOut->baseAlign =
+ pipes * pTileInfo->bankWidth * pTileInfo->banks *
pTileInfo->bankHeight * tileSize;
- HwlComputeSurfaceAlignmentsMacroTiled(tileMode, bpp, flags, mipLevel,
numSamples,
- pTileInfo, pBaseAlign,
pPitchAlign, pHeightAlign,
- pMacroTileWidth,
pMacroTileHeight);
+ HwlComputeSurfaceAlignmentsMacroTiled(tileMode, bpp, flags, mipLevel,
numSamples, pOut);
}
return valid;
}
/**
****************************************************************************************************
* EgBasedLib::SanityCheckMacroTiled
*
* @brief
@@ -1162,30 +1147,26 @@ BOOL_32 EgBasedLib::HwlGetAlignmentInfoMacroTiled(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] create
surface info
UINT_32* pPitchAlign, ///< [out] pitch
alignment
UINT_32* pHeightAlign, ///< [out] height
alignment
UINT_32* pSizeAlign ///< [out] size
alignment
) const
{
BOOL_32 valid = TRUE;
ADDR_ASSERT(IsMacroTiled(pIn->tileMode));
- UINT_32 baseAlign;
- UINT_32 pitchAlign;
- UINT_32 heightAlign;
- UINT_32 macroTileWidth;
- UINT_32 macroTileHeight;
UINT_32 numSamples = (pIn->numFrags == 0) ? pIn->numSamples :
pIn->numFrags;
ADDR_ASSERT(pIn->pTileInfo);
ADDR_TILEINFO tileInfo = *pIn->pTileInfo;
ADDR_COMPUTE_SURFACE_INFO_OUTPUT out = {0};
+ out.pTileInfo = &tileInfo;
if (UseTileIndex(pIn->tileIndex))
{
out.tileIndex = pIn->tileIndex;
out.macroModeIndex = TileIndexInvalid;
}
HwlSetupTileInfo(pIn->tileMode,
pIn->flags,
pIn->bpp,
@@ -1195,32 +1176,27 @@ BOOL_32 EgBasedLib::HwlGetAlignmentInfoMacroTiled(
&tileInfo,
&tileInfo,
pIn->tileType,
&out);
valid = ComputeSurfaceAlignmentsMacroTiled(pIn->tileMode,
pIn->bpp,
pIn->flags,
pIn->mipLevel,
numSamples,
- &tileInfo,
- &baseAlign,
- &pitchAlign,
- &heightAlign,
- ¯oTileWidth,
- ¯oTileHeight);
+ &out);
if (valid)
{
- *pPitchAlign = pitchAlign;
- *pHeightAlign = heightAlign;
- *pSizeAlign = baseAlign;
+ *pPitchAlign = out.pitchAlign;
+ *pHeightAlign = out.heightAlign;
+ *pSizeAlign = out.baseAlign;
}
return valid;
}
/**
****************************************************************************************************
* EgBasedLib::HwlDegradeThickTileMode
*
* @brief
diff --git a/src/amd/addrlib/r800/egbaddrlib.h
b/src/amd/addrlib/r800/egbaddrlib.h
index 50fd3d9..dbe712a 100644
--- a/src/amd/addrlib/r800/egbaddrlib.h
+++ b/src/amd/addrlib/r800/egbaddrlib.h
@@ -296,23 +296,21 @@ protected:
UINT_32 log2BytesPP, AddrTileMode tileMode, AddrTileType microTileType,
ADDR_TILEINFO* pTileInfo, ADDR_EQUATION* pEquation) const;
// Static functions
static BOOL_32 IsTileInfoAllZero(ADDR_TILEINFO* pTileInfo);
static UINT_32 ComputeFmaskNumPlanesFromNumSamples(UINT_32 numSamples);
static UINT_32 ComputeFmaskResolvedBppFromNumSamples(UINT_32 numSamples);
virtual VOID HwlComputeSurfaceAlignmentsMacroTiled(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
- UINT_32 mipLevel, UINT_32 numSamples, ADDR_TILEINFO* pTileInfo,
- UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign,
- UINT_32* pMacroTileWidth, UINT_32* pMacroTileHeight) const
+ UINT_32 mipLevel, UINT_32 numSamples,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const
{
}
private:
BOOL_32 ComputeSurfaceInfoLinear(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut,
UINT_32 padDims) const;
@@ -333,23 +331,21 @@ private:
UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign)
const;
BOOL_32 ComputeSurfaceAlignmentsMicroTiled(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32 mipLevel, UINT_32 numSamples,
UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign)
const;
BOOL_32 ComputeSurfaceAlignmentsMacroTiled(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32 mipLevel, UINT_32 numSamples,
- ADDR_TILEINFO* pTileInfo,
- UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign,
- UINT_32* pMacroTileWidth, UINT_32* pMacroTileHeight) const;
+ ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
/// Surface addressing functions
UINT_64 DispatchComputeSurfaceAddrFromCoord(
const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
VOID DispatchComputeSurfaceCoordFromAddr(
const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const;
diff --git a/src/amd/addrlib/r800/siaddrlib.cpp
b/src/amd/addrlib/r800/siaddrlib.cpp
index 299951e..c1f6dac 100644
--- a/src/amd/addrlib/r800/siaddrlib.cpp
+++ b/src/amd/addrlib/r800/siaddrlib.cpp
@@ -3374,45 +3374,40 @@ ADDR_E_RETURNCODE SiLib::HwlGetMaxAlignments(
*
* @brief
* Hardware layer function to compute alignment request for macro tile
mode
*
* @return
* N/A
*
****************************************************************************************************
*/
VOID SiLib::HwlComputeSurfaceAlignmentsMacroTiled(
- AddrTileMode tileMode, ///< [in] tile mode
- UINT_32 bpp, ///< [in] bits per pixel
- ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
- UINT_32 mipLevel, ///< [in] mip level
- UINT_32 numSamples, ///< [in] number of samples
- ADDR_TILEINFO* pTileInfo, ///< [in,out] bank structure.
- UINT_32* pBaseAlign, ///< [out] base address alignment
in bytes
- UINT_32* pPitchAlign, ///< [out] pitch alignment in
pixels
- UINT_32* pHeightAlign, ///< [out] height alignment in
pixels
- UINT_32* pMacroTileWidth, ///< [out] macro tile width in
pixels
- UINT_32* pMacroTileHeight ///< [out] macro tile height in
pixels
+ AddrTileMode tileMode, ///< [in] tile mode
+ UINT_32 bpp, ///< [in] bits per
pixel
+ ADDR_SURFACE_FLAGS flags, ///< [in] surface
flags
+ UINT_32 mipLevel, ///< [in] mip level
+ UINT_32 numSamples, ///< [in] number of
samples
+ ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [in,out]
Surface output
) const
{
if ((mipLevel == 0) && (flags.prt))
{
- UINT_32 macroTileSize = (*pMacroTileWidth) * (*pMacroTileHeight) *
numSamples * bpp / 8;
+ UINT_32 macroTileSize = pOut->blockWidth * pOut->blockHeight *
numSamples * bpp / 8;
if (macroTileSize < PrtTileSize)
{
UINT_32 numMacroTiles = PrtTileSize / macroTileSize;
ADDR_ASSERT((PrtTileSize % macroTileSize) == 0);
- *pPitchAlign *= numMacroTiles;
- *pBaseAlign *= numMacroTiles;
+ pOut->pitchAlign *= numMacroTiles;
+ pOut->baseAlign *= numMacroTiles;
}
}
}
/**
****************************************************************************************************
* SiLib::InitEquationTable
*
* @brief
* Initialize Equation table.
diff --git a/src/amd/addrlib/r800/siaddrlib.h b/src/amd/addrlib/r800/siaddrlib.h
index 53ec68b..6daaa23 100644
--- a/src/amd/addrlib/r800/siaddrlib.h
+++ b/src/amd/addrlib/r800/siaddrlib.h
@@ -242,23 +242,21 @@ protected:
UINT_32 bankHeightAlign, UINT_32 pipes,
ADDR_TILEINFO* pTileInfo) const
{
return TRUE;
}
virtual ADDR_E_RETURNCODE
HwlGetMaxAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const;
virtual VOID HwlComputeSurfaceAlignmentsMacroTiled(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
- UINT_32 mipLevel, UINT_32 numSamples, ADDR_TILEINFO* pTileInfo,
- UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign,
- UINT_32* pMacroTileWidth, UINT_32* pMacroTileHeight) const;
+ UINT_32 mipLevel, UINT_32 numSamples,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
// Get equation table pointer and number of equations
virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION**
ppEquationTable) const
{
*ppEquationTable = m_equationTable;
return m_numEquations;
}
// Check if it is supported for given bpp and tile config to generate an
equation
@@ -279,21 +277,21 @@ protected:
const TileConfig* GetTileSetting(
UINT_32 index) const;
// Initialize equation table
VOID InitEquationTable();
UINT_32 GetPipePerSurf(AddrPipeCfg pipeConfig) const;
static const UINT_32 TileTableSize = 32;
- TileConfig m_tileTable[TileTableSize];
+ TileConfig m_tileTable[TileTableSize];
UINT_32 m_noOfEntries;
// Max number of bpp (8bpp/16bpp/32bpp/64bpp/128bpp)
static const UINT_32 MaxNumElementBytes = 5;
// More than half slots in tile mode table can't support equation
static const UINT_32 EquationTableSize = (MaxNumElementBytes *
TileTableSize) / 2;
// Equation table
ADDR_EQUATION m_equationTable[EquationTableSize];
UINT_32 m_blockWidth[EquationTableSize];
UINT_32 m_blockHeight[EquationTableSize];
--
2.7.4
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
