From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeonsi/cik_sdma.c | 4 ++--
src/gallium/drivers/radeonsi/si_perfcounter.c | 1 +
src/gallium/drivers/radeonsi/si_pipe.c | 1 +
src/gallium/drivers/radeonsi/si_state_shaders.c | 1 +
4 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/cik_sdma.c
b/src/gallium/drivers/radeonsi/cik_sdma.c
index bee35cd..fdcf22f 100644
--- a/src/gallium/drivers/radeonsi/cik_sdma.c
+++ b/src/gallium/drivers/radeonsi/cik_sdma.c
@@ -422,23 +422,23 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
src_mode >= RADEON_SURF_MODE_1D &&
/* check if these fit into the bitfields */
src_address % 256 == 0 &&
dst_address % 256 == 0 &&
rsrc->surface.tile_split <= 4096 &&
rdst->surface.tile_split <= 4096 &&
dstx % 8 == 0 &&
dsty % 8 == 0 &&
srcx % 8 == 0 &&
srcy % 8 == 0 &&
- /* this can either be equal, or display->rotated (VI only) */
+ /* this can either be equal, or display->rotated (VI+ only) */
(src_micro_mode == dst_micro_mode ||
- (sctx->b.chip_class == VI &&
+ (sctx->b.chip_class >= VI &&
src_micro_mode == V_009910_ADDR_SURF_DISPLAY_MICRO_TILING &&
dst_micro_mode == V_009910_ADDR_SURF_ROTATED_MICRO_TILING))) {
assert(src_pitch % 8 == 0);
assert(dst_pitch % 8 == 0);
assert(src_slice_pitch % 64 == 0);
assert(dst_slice_pitch % 64 == 0);
unsigned src_pitch_tile_max = src_pitch / 8 - 1;
unsigned dst_pitch_tile_max = dst_pitch / 8 - 1;
unsigned src_slice_tile_max = src_slice_pitch / 64 - 1;
unsigned dst_slice_tile_max = dst_slice_pitch / 64 - 1;
diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c
b/src/gallium/drivers/radeonsi/si_perfcounter.c
index 00db2c4..41dd52e 100644
--- a/src/gallium/drivers/radeonsi/si_perfcounter.c
+++ b/src/gallium/drivers/radeonsi/si_perfcounter.c
@@ -665,20 +665,21 @@ void si_init_perfcounters(struct si_screen *screen)
switch (screen->b.chip_class) {
case CIK:
blocks = groups_CIK;
num_blocks = ARRAY_SIZE(groups_CIK);
break;
case VI:
blocks = groups_VI;
num_blocks = ARRAY_SIZE(groups_VI);
break;
case SI:
+ case GFX9:
default:
return; /* not implemented */
}
if (screen->b.info.max_sh_per_se != 1) {
/* This should not happen on non-SI chips. */
fprintf(stderr, "si_init_perfcounters: max_sh_per_se = %d not "
"supported (inaccurate performance counters)\n",
screen->b.info.max_sh_per_se);
}
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index c66203e..7f0b445 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -724,20 +724,21 @@ static bool si_init_gs_info(struct si_screen *sscreen)
case CHIP_TAHITI:
case CHIP_PITCAIRN:
case CHIP_VERDE:
case CHIP_BONAIRE:
case CHIP_HAWAII:
case CHIP_TONGA:
case CHIP_FIJI:
case CHIP_POLARIS10:
case CHIP_POLARIS11:
case CHIP_POLARIS12:
+ case CHIP_VEGA10:
sscreen->gs_table_depth = 32;
return true;
default:
return false;
}
}
static void si_handle_env_var_force_family(struct si_screen *sscreen)
{
const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 3596f5a..f778cd7 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -2382,20 +2382,21 @@ static void si_init_tess_factor_ring(struct si_context
*sctx)
case 4096:
offchip_granularity = V_03093C_X_4K_DWORDS;
break;
}
switch (sctx->b.chip_class) {
case SI:
max_offchip_buffers = MIN2(max_offchip_buffers, 126);
break;
case CIK:
+ case GFX9:
max_offchip_buffers = MIN2(max_offchip_buffers, 508);
break;
case VI:
default:
max_offchip_buffers = MIN2(max_offchip_buffers, 512);
break;
}
assert(!sctx->tf_ring);
sctx->tf_ring = r600_aligned_buffer_create(sctx->b.b.screen,
--
2.7.4
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
