Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
On 09/12/16 10:54, Chris Wilson wrote:
Rename brw_load_register_reg to include the width (32bits) similar to all the other register routines. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> --- src/mesa/drivers/dri/i965/brw_pipelined_register.c | 2 +- src/mesa/drivers/dri/i965/brw_pipelined_register.h | 6 +++--- src/mesa/drivers/dri/i965/hsw_queryobj.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_pipelined_register.c b/src/mesa/drivers/dri/i965/brw_pipelined_register.c index b143bac04e..0b226035e7 100644 --- a/src/mesa/drivers/dri/i965/brw_pipelined_register.c +++ b/src/mesa/drivers/dri/i965/brw_pipelined_register.c @@ -175,7 +175,7 @@ brw_load_register_imm64(struct brw_context *brw, uint32_t reg, uint64_t imm) * Copies a 32-bit register. */ void -brw_load_register_reg(struct brw_context *brw, uint32_t src, uint32_t dest) +brw_load_register_reg32(struct brw_context *brw, uint32_t src, uint32_t dest) { assert(brw->gen >= 8 || brw->is_haswell);diff --git a/src/mesa/drivers/dri/i965/brw_pipelined_register.h b/src/mesa/drivers/dri/i965/brw_pipelined_register.hindex 94d52433a1..7730f4cad7 100644 --- a/src/mesa/drivers/dri/i965/brw_pipelined_register.h +++ b/src/mesa/drivers/dri/i965/brw_pipelined_register.h @@ -53,9 +53,9 @@ void brw_load_register_imm64(struct brw_context *brw, uint32_t reg, uint64_t imm);-void brw_load_register_reg(struct brw_context *brw,- uint32_t src, - uint32_t dest); +void brw_load_register_reg32(struct brw_context *brw, + uint32_t src, + uint32_t dest); void brw_load_register_reg64(struct brw_context *brw, uint32_t src, uint32_t dest); diff --git a/src/mesa/drivers/dri/i965/hsw_queryobj.c b/src/mesa/drivers/dri/i965/hsw_queryobj.c index c3eeafc091..e9a6f459a1 100644 --- a/src/mesa/drivers/dri/i965/hsw_queryobj.c +++ b/src/mesa/drivers/dri/i965/hsw_queryobj.c @@ -156,7 +156,7 @@ static void shr_gpr0_by_2_bits(struct brw_context *brw) { shl_gpr0_by_30_bits(brw); - brw_load_register_reg(brw, HSW_CS_GPR(0) + 4, HSW_CS_GPR(0)); + brw_load_register_reg32(brw, HSW_CS_GPR(0) + 4, HSW_CS_GPR(0)); brw_load_register_imm32(brw, HSW_CS_GPR(0) + 4, 0); }
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