The domains used are immaterial, and we should never be marking the read
from the buffer as a write, so stop passing them around from the caller
and choose the appropriate read domain when writing.
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/brw_compute.c | 27 +++++----------
src/mesa/drivers/dri/i965/brw_conditional_render.c | 14 ++------
src/mesa/drivers/dri/i965/brw_context.h | 10 +++---
src/mesa/drivers/dri/i965/brw_draw.c | 38 +++++++++-------------
src/mesa/drivers/dri/i965/hsw_queryobj.c | 29 ++++-------------
src/mesa/drivers/dri/i965/hsw_sol.c | 14 +++-----
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 19 +++++------
7 files changed, 48 insertions(+), 103 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_compute.c
b/src/mesa/drivers/dri/i965/brw_compute.c
index 16b5df7ca4..51cd45df7a 100644
--- a/src/mesa/drivers/dri/i965/brw_compute.c
+++ b/src/mesa/drivers/dri/i965/brw_compute.c
@@ -40,15 +40,12 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw)
GLintptr indirect_offset = brw->compute.num_work_groups_offset;
drm_intel_bo *bo = brw->compute.num_work_groups_bo;
- brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMX, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
- indirect_offset + 0);
- brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMY, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
- indirect_offset + 4);
- brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMZ, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
- indirect_offset + 8);
+ brw_load_register_mem32(brw,
+ GEN7_GPGPU_DISPATCHDIMX, bo, indirect_offset + 0);
+ brw_load_register_mem32(brw,
+ GEN7_GPGPU_DISPATCHDIMY, bo, indirect_offset + 4);
+ brw_load_register_mem32(brw,
+ GEN7_GPGPU_DISPATCHDIMZ, bo, indirect_offset + 8);
if (brw->gen > 7)
return;
@@ -65,9 +62,7 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw)
ADVANCE_BATCH();
/* Load compute_dispatch_indirect_x_size into SRC0 */
- brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- indirect_offset + 0);
+ brw_load_register_mem32(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 0);
/* predicate = (compute_dispatch_indirect_x_size == 0); */
BEGIN_BATCH(1);
@@ -78,9 +73,7 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw)
ADVANCE_BATCH();
/* Load compute_dispatch_indirect_y_size into SRC0 */
- brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- indirect_offset + 4);
+ brw_load_register_mem32(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 4);
/* predicate |= (compute_dispatch_indirect_y_size == 0); */
BEGIN_BATCH(1);
@@ -91,9 +84,7 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw)
ADVANCE_BATCH();
/* Load compute_dispatch_indirect_z_size into SRC0 */
- brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- indirect_offset + 8);
+ brw_load_register_mem32(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 8);
/* predicate |= (compute_dispatch_indirect_z_size == 0); */
BEGIN_BATCH(1);
diff --git a/src/mesa/drivers/dri/i965/brw_conditional_render.c
b/src/mesa/drivers/dri/i965/brw_conditional_render.c
index 122a4ecc0f..8574fc1aeb 100644
--- a/src/mesa/drivers/dri/i965/brw_conditional_render.c
+++ b/src/mesa/drivers/dri/i965/brw_conditional_render.c
@@ -62,18 +62,8 @@ set_predicate_for_result(struct brw_context *brw,
*/
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE);
- brw_load_register_mem64(brw,
- MI_PREDICATE_SRC0,
- query->bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- 0, /* write domain */
- 0 /* offset */);
- brw_load_register_mem64(brw,
- MI_PREDICATE_SRC1,
- query->bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- 0, /* write domain */
- 8 /* offset */);
+ brw_load_register_mem64(brw, MI_PREDICATE_SRC0, query->bo, 0 /* offset */);
+ brw_load_register_mem64(brw, MI_PREDICATE_SRC1, query->bo, 8 /* offset */);
if (inverted)
load_op = MI_PREDICATE_LOADOP_LOAD;
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 550eefedcc..77a5f8b879 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1363,15 +1363,13 @@ void brw_init_conditional_render_functions(struct
dd_function_table *functions);
bool brw_check_conditional_render(struct brw_context *brw);
/** intel_batchbuffer.c */
-void brw_load_register_mem(struct brw_context *brw,
- uint32_t reg,
- drm_intel_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
- uint32_t offset);
+void brw_load_register_mem32(struct brw_context *brw,
+ uint32_t reg,
+ drm_intel_bo *bo,
+ uint32_t offset);
void brw_load_register_mem64(struct brw_context *brw,
uint32_t reg,
drm_intel_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
uint32_t offset);
void brw_store_register_mem32(struct brw_context *brw,
drm_intel_bo *bo, uint32_t reg, uint32_t offset);
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index d4cc2235a4..52589d0d13 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -203,10 +203,9 @@ brw_emit_prim(struct brw_context *brw,
if (xfb_obj) {
indirect_flag = GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE;
- brw_load_register_mem(brw, GEN7_3DPRIM_VERTEX_COUNT,
- xfb_obj->prim_count_bo,
- I915_GEM_DOMAIN_VERTEX, 0,
- stream * sizeof(uint32_t));
+ brw_load_register_mem32(brw, GEN7_3DPRIM_VERTEX_COUNT,
+ xfb_obj->prim_count_bo,
+ stream * sizeof(uint32_t));
BEGIN_BATCH(9);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (9 - 2));
OUT_BATCH(GEN7_3DPRIM_INSTANCE_COUNT);
@@ -226,27 +225,20 @@ brw_emit_prim(struct brw_context *brw,
indirect_flag = GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE;
- brw_load_register_mem(brw, GEN7_3DPRIM_VERTEX_COUNT, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
- prim->indirect_offset + 0);
- brw_load_register_mem(brw, GEN7_3DPRIM_INSTANCE_COUNT, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
- prim->indirect_offset + 4);
-
- brw_load_register_mem(brw, GEN7_3DPRIM_START_VERTEX, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
- prim->indirect_offset + 8);
+ brw_load_register_mem32(brw, GEN7_3DPRIM_VERTEX_COUNT, bo,
+ prim->indirect_offset + 0);
+ brw_load_register_mem32(brw, GEN7_3DPRIM_INSTANCE_COUNT, bo,
+ prim->indirect_offset + 4);
+ brw_load_register_mem32(brw, GEN7_3DPRIM_START_VERTEX, bo,
+ prim->indirect_offset + 8);
if (prim->indexed) {
- brw_load_register_mem(brw, GEN7_3DPRIM_BASE_VERTEX, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
- prim->indirect_offset + 12);
- brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
- prim->indirect_offset + 16);
+ brw_load_register_mem32(brw, GEN7_3DPRIM_BASE_VERTEX, bo,
+ prim->indirect_offset + 12);
+ brw_load_register_mem32(brw, GEN7_3DPRIM_START_INSTANCE, bo,
+ prim->indirect_offset + 16);
} else {
- brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
- prim->indirect_offset + 12);
+ brw_load_register_mem32(brw, GEN7_3DPRIM_START_INSTANCE, bo,
+ prim->indirect_offset + 12);
BEGIN_BATCH(3);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX);
diff --git a/src/mesa/drivers/dri/i965/hsw_queryobj.c
b/src/mesa/drivers/dri/i965/hsw_queryobj.c
index 0da2c3d388..0c558c5624 100644
--- a/src/mesa/drivers/dri/i965/hsw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/hsw_queryobj.c
@@ -199,11 +199,7 @@ hsw_result_to_gpr0(struct gl_context *ctx, struct
brw_query_object *query,
if (pname == GL_QUERY_RESULT_AVAILABLE) {
/* The query result availability is stored at offset 0 of the buffer. */
brw_load_register_mem64(brw,
- HSW_CS_GPR(0),
- query->bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION,
- 2 * sizeof(uint64_t));
+ HSW_CS_GPR(0), query->bo, 2 * sizeof(uint64_t));
return;
}
@@ -218,24 +214,12 @@ hsw_result_to_gpr0(struct gl_context *ctx, struct
brw_query_object *query,
if (query->Base.Target == GL_TIMESTAMP) {
brw_load_register_mem64(brw,
- HSW_CS_GPR(0),
- query->bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION,
- 0 * sizeof(uint64_t));
+ HSW_CS_GPR(0), query->bo, 0 * sizeof(uint64_t));
} else {
brw_load_register_mem64(brw,
- HSW_CS_GPR(1),
- query->bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION,
- 0 * sizeof(uint64_t));
+ HSW_CS_GPR(1), query->bo, 0 * sizeof(uint64_t));
brw_load_register_mem64(brw,
- HSW_CS_GPR(2),
- query->bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION,
- 1 * sizeof(uint64_t));
+ HSW_CS_GPR(2), query->bo, 1 * sizeof(uint64_t));
BEGIN_BATCH(5);
OUT_BATCH(HSW_MI_MATH | (5 - 2));
@@ -304,9 +288,8 @@ set_predicate(struct brw_context *brw, drm_intel_bo
*query_bo)
brw_load_register_imm64(brw, MI_PREDICATE_SRC1, 0ull);
/* Load query availability into SRC0 */
- brw_load_register_mem64(brw, MI_PREDICATE_SRC0, query_bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- 2 * sizeof(uint64_t));
+ brw_load_register_mem64(brw,
+ MI_PREDICATE_SRC0, query_bo, 2 * sizeof(uint64_t));
/* predicate = !(query_availability == 0); */
BEGIN_BATCH(1);
diff --git a/src/mesa/drivers/dri/i965/hsw_sol.c
b/src/mesa/drivers/dri/i965/hsw_sol.c
index 2f1112699b..32e70c9d55 100644
--- a/src/mesa/drivers/dri/i965/hsw_sol.c
+++ b/src/mesa/drivers/dri/i965/hsw_sol.c
@@ -91,15 +91,11 @@ tally_prims_written(struct brw_context *brw,
for (int i = 0; i < BRW_MAX_XFB_STREAMS; i++) {
/* GPR0 = Tally */
brw_load_register_imm32(brw, HSW_CS_GPR(0) + 4, 0);
- brw_load_register_mem(brw, HSW_CS_GPR(0), obj->prim_count_bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION,
- TALLY_OFFSET + i * sizeof(uint32_t));
+ brw_load_register_mem32(brw, HSW_CS_GPR(0), obj->prim_count_bo,
+ TALLY_OFFSET + i * sizeof(uint32_t));
if (!obj->base.Paused) {
/* GPR1 = Start Snapshot */
brw_load_register_mem64(brw, HSW_CS_GPR(1), obj->prim_count_bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION,
START_OFFSET + i * sizeof(uint64_t));
/* GPR2 = Ending Snapshot */
brw_load_register_reg64(brw, GEN7_SO_NUM_PRIMS_WRITTEN(i),
HSW_CS_GPR(2));
@@ -228,10 +224,8 @@ hsw_resume_transform_feedback(struct gl_context *ctx,
if (brw->is_haswell) {
/* Reload the SOL buffer offset registers. */
for (int i = 0; i < BRW_MAX_XFB_STREAMS; i++)
- brw_load_register_mem(brw, GEN7_SO_WRITE_OFFSET(i),
- brw_obj->offset_bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- i * sizeof(uint32_t));
+ brw_load_register_mem32(brw, GEN7_SO_WRITE_OFFSET(i),
+ brw_obj->offset_bo, i * sizeof(uint32_t));
}
/* Store the new starting value of the SO_NUM_PRIMS_WRITTEN counters. */
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index f136fae6cc..69b9c586d5 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -493,7 +493,6 @@ static void
load_sized_register_mem(struct brw_context *brw,
uint32_t reg,
drm_intel_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
uint32_t offset,
int size)
{
@@ -507,7 +506,7 @@ load_sized_register_mem(struct brw_context *brw,
for (i = 0; i < size; i++) {
OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (4 - 2));
OUT_BATCH(reg + i * 4);
- OUT_RELOC64(bo, read_domains, write_domain, offset + i * 4);
+ OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, offset + i * 4);
}
ADVANCE_BATCH();
} else {
@@ -515,30 +514,28 @@ load_sized_register_mem(struct brw_context *brw,
for (i = 0; i < size; i++) {
OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
OUT_BATCH(reg + i * 4);
- OUT_RELOC(bo, read_domains, write_domain, offset + i * 4);
+ OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, offset + i * 4);
}
ADVANCE_BATCH();
}
}
void
-brw_load_register_mem(struct brw_context *brw,
- uint32_t reg,
- drm_intel_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
- uint32_t offset)
+brw_load_register_mem32(struct brw_context *brw,
+ uint32_t reg,
+ drm_intel_bo *bo,
+ uint32_t offset)
{
- load_sized_register_mem(brw, reg, bo, read_domains, write_domain, offset,
1);
+ load_sized_register_mem(brw, reg, bo, offset, 1);
}
void
brw_load_register_mem64(struct brw_context *brw,
uint32_t reg,
drm_intel_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
uint32_t offset)
{
- load_sized_register_mem(brw, reg, bo, read_domains, write_domain, offset,
2);
+ load_sized_register_mem(brw, reg, bo, offset, 2);
}
/*
--
2.11.0
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