My ulterior motive is to kill intel_batchbuffer.[ch] and moving
discrete pieces of functionality into their own files is a small step
towards that goal.
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/Makefile.sources | 2 +
src/mesa/drivers/dri/i965/brw_compute.c | 1 +
src/mesa/drivers/dri/i965/brw_conditional_render.c | 2 +
src/mesa/drivers/dri/i965/brw_context.h | 26 ---
src/mesa/drivers/dri/i965/brw_draw.c | 1 +
.../drivers/dri/i965/brw_performance_monitor.c | 2 +
src/mesa/drivers/dri/i965/brw_pipelined_register.c | 252 +++++++++++++++++++++
src/mesa/drivers/dri/i965/brw_pipelined_register.h | 76 +++++++
src/mesa/drivers/dri/i965/brw_state_upload.c | 1 +
src/mesa/drivers/dri/i965/gen6_queryobj.c | 1 +
src/mesa/drivers/dri/i965/gen7_l3_state.c | 2 +
src/mesa/drivers/dri/i965/gen7_sol_state.c | 2 +
src/mesa/drivers/dri/i965/gen8_depth_state.c | 1 +
src/mesa/drivers/dri/i965/hsw_queryobj.c | 2 +
src/mesa/drivers/dri/i965/hsw_sol.c | 2 +
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 224 ------------------
16 files changed, 347 insertions(+), 250 deletions(-)
create mode 100644 src/mesa/drivers/dri/i965/brw_pipelined_register.c
create mode 100644 src/mesa/drivers/dri/i965/brw_pipelined_register.h
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources
b/src/mesa/drivers/dri/i965/Makefile.sources
index 1c33ea55fa..49044db169 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -137,6 +137,8 @@ i965_FILES = \
brw_object_purgeable.c \
brw_performance_monitor.c \
brw_pipe_control.c \
+ brw_pipelined_register.c \
+ brw_pipelined_register.h \
brw_program.c \
brw_program.h \
brw_program_cache.c \
diff --git a/src/mesa/drivers/dri/i965/brw_compute.c
b/src/mesa/drivers/dri/i965/brw_compute.c
index 51cd45df7a..d63ebbe588 100644
--- a/src/mesa/drivers/dri/i965/brw_compute.c
+++ b/src/mesa/drivers/dri/i965/brw_compute.c
@@ -28,6 +28,7 @@
#include "main/state.h"
#include "brw_context.h"
#include "brw_draw.h"
+#include "brw_pipelined_register.h"
#include "brw_state.h"
#include "intel_batchbuffer.h"
#include "intel_buffer_objects.h"
diff --git a/src/mesa/drivers/dri/i965/brw_conditional_render.c
b/src/mesa/drivers/dri/i965/brw_conditional_render.c
index 8574fc1aeb..6ad218be55 100644
--- a/src/mesa/drivers/dri/i965/brw_conditional_render.c
+++ b/src/mesa/drivers/dri/i965/brw_conditional_render.c
@@ -35,6 +35,8 @@
#include "brw_context.h"
#include "brw_defines.h"
+#include "brw_pipelined_register.h"
+
#include "intel_batchbuffer.h"
static void
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 77a5f8b879..428f5773c1 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1362,32 +1362,6 @@ void hsw_init_queryobj_functions(struct
dd_function_table *functions);
void brw_init_conditional_render_functions(struct dd_function_table
*functions);
bool brw_check_conditional_render(struct brw_context *brw);
-/** intel_batchbuffer.c */
-void brw_load_register_mem32(struct brw_context *brw,
- uint32_t reg,
- drm_intel_bo *bo,
- uint32_t offset);
-void brw_load_register_mem64(struct brw_context *brw,
- uint32_t reg,
- drm_intel_bo *bo,
- uint32_t offset);
-void brw_store_register_mem32(struct brw_context *brw,
- drm_intel_bo *bo, uint32_t reg, uint32_t offset);
-void brw_store_register_mem64(struct brw_context *brw,
- drm_intel_bo *bo, uint32_t reg, uint32_t offset);
-void brw_load_register_imm32(struct brw_context *brw,
- uint32_t reg, uint32_t imm);
-void brw_load_register_imm64(struct brw_context *brw,
- uint32_t reg, uint64_t imm);
-void brw_load_register_reg(struct brw_context *brw, uint32_t src,
- uint32_t dest);
-void brw_load_register_reg64(struct brw_context *brw, uint32_t src,
- uint32_t dest);
-void brw_store_data_imm32(struct brw_context *brw, drm_intel_bo *bo,
- uint32_t offset, uint32_t imm);
-void brw_store_data_imm64(struct brw_context *brw, drm_intel_bo *bo,
- uint32_t offset, uint64_t imm);
-
/*======================================================================
* brw_state_dump.c
*/
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index b78e73516e..44d5dac1fc 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -44,6 +44,7 @@
#include "brw_draw.h"
#include "brw_defines.h"
#include "brw_context.h"
+#include "brw_pipelined_register.h"
#include "brw_state.h"
#include "brw_vs.h"
diff --git a/src/mesa/drivers/dri/i965/brw_performance_monitor.c
b/src/mesa/drivers/dri/i965/brw_performance_monitor.c
index f8e50e10fa..1b991bfafa 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_monitor.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_monitor.c
@@ -54,6 +54,8 @@
#include "brw_context.h"
#include "brw_defines.h"
+#include "brw_pipelined_register.h"
+
#include "intel_batchbuffer.h"
#define FILE_DEBUG_FLAG DEBUG_PERFMON
diff --git a/src/mesa/drivers/dri/i965/brw_pipelined_register.c
b/src/mesa/drivers/dri/i965/brw_pipelined_register.c
new file mode 100644
index 0000000000..b143bac04e
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/brw_pipelined_register.c
@@ -0,0 +1,252 @@
+/*
+ * Copyright © 2010-2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "brw_context.h"
+#include "brw_defines.h"
+#include "brw_pipelined_register.h"
+
+#include "intel_batchbuffer.h"
+
+static void
+load_sized_register_mem(struct brw_context *brw,
+ uint32_t reg,
+ drm_intel_bo *bo,
+ uint32_t offset,
+ int size)
+{
+ int i;
+
+ /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
+ assert(brw->gen >= 7);
+
+ if (brw->gen >= 8) {
+ BEGIN_BATCH(4 * size);
+ for (i = 0; i < size; i++) {
+ OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (4 - 2));
+ OUT_BATCH(reg + i * 4);
+ OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, offset + i * 4);
+ }
+ ADVANCE_BATCH();
+ } else {
+ BEGIN_BATCH(3 * size);
+ for (i = 0; i < size; i++) {
+ OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
+ OUT_BATCH(reg + i * 4);
+ OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, offset + i * 4);
+ }
+ ADVANCE_BATCH();
+ }
+}
+
+void
+brw_load_register_mem32(struct brw_context *brw,
+ uint32_t reg,
+ drm_intel_bo *bo,
+ uint32_t offset)
+{
+ load_sized_register_mem(brw, reg, bo, offset, 1);
+}
+
+void
+brw_load_register_mem64(struct brw_context *brw,
+ uint32_t reg,
+ drm_intel_bo *bo,
+ uint32_t offset)
+{
+ load_sized_register_mem(brw, reg, bo, offset, 2);
+}
+
+/*
+ * Write an arbitrary 32-bit register to a buffer via MI_STORE_REGISTER_MEM.
+ */
+void
+brw_store_register_mem32(struct brw_context *brw,
+ drm_intel_bo *bo, uint32_t reg, uint32_t offset)
+{
+ assert(brw->gen >= 6);
+
+ if (brw->gen >= 8) {
+ BEGIN_BATCH(4);
+ OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2));
+ OUT_BATCH(reg);
+ OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ offset);
+ ADVANCE_BATCH();
+ } else {
+ BEGIN_BATCH(3);
+ OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
+ OUT_BATCH(reg);
+ OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ offset);
+ ADVANCE_BATCH();
+ }
+}
+
+/*
+ * Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM.
+ */
+void
+brw_store_register_mem64(struct brw_context *brw,
+ drm_intel_bo *bo, uint32_t reg, uint32_t offset)
+{
+ assert(brw->gen >= 6);
+
+ /* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to
+ * read a full 64-bit register, we need to do two of them.
+ */
+ if (brw->gen >= 8) {
+ BEGIN_BATCH(8);
+ OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2));
+ OUT_BATCH(reg);
+ OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ offset);
+ OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2));
+ OUT_BATCH(reg + sizeof(uint32_t));
+ OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ offset + sizeof(uint32_t));
+ ADVANCE_BATCH();
+ } else {
+ BEGIN_BATCH(6);
+ OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
+ OUT_BATCH(reg);
+ OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ offset);
+ OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
+ OUT_BATCH(reg + sizeof(uint32_t));
+ OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ offset + sizeof(uint32_t));
+ ADVANCE_BATCH();
+ }
+}
+
+/*
+ * Write a 32-bit register using immediate data.
+ */
+void
+brw_load_register_imm32(struct brw_context *brw, uint32_t reg, uint32_t imm)
+{
+ assert(brw->gen >= 6);
+
+ BEGIN_BATCH(3);
+ OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
+ OUT_BATCH(reg);
+ OUT_BATCH(imm);
+ ADVANCE_BATCH();
+}
+
+/*
+ * Write a 64-bit register using immediate data.
+ */
+void
+brw_load_register_imm64(struct brw_context *brw, uint32_t reg, uint64_t imm)
+{
+ assert(brw->gen >= 6);
+
+ BEGIN_BATCH(5);
+ OUT_BATCH(MI_LOAD_REGISTER_IMM | (5 - 2));
+ OUT_BATCH(reg);
+ OUT_BATCH(imm & 0xffffffff);
+ OUT_BATCH(reg + 4);
+ OUT_BATCH(imm >> 32);
+ ADVANCE_BATCH();
+}
+
+/*
+ * Copies a 32-bit register.
+ */
+void
+brw_load_register_reg(struct brw_context *brw, uint32_t src, uint32_t dest)
+{
+ assert(brw->gen >= 8 || brw->is_haswell);
+
+ BEGIN_BATCH(3);
+ OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2));
+ OUT_BATCH(src);
+ OUT_BATCH(dest);
+ ADVANCE_BATCH();
+}
+
+/*
+ * Copies a 64-bit register.
+ */
+void
+brw_load_register_reg64(struct brw_context *brw, uint32_t src, uint32_t dest)
+{
+ assert(brw->gen >= 8 || brw->is_haswell);
+
+ BEGIN_BATCH(6);
+ OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2));
+ OUT_BATCH(src);
+ OUT_BATCH(dest);
+ OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2));
+ OUT_BATCH(src + sizeof(uint32_t));
+ OUT_BATCH(dest + sizeof(uint32_t));
+ ADVANCE_BATCH();
+}
+
+/*
+ * Write 32-bits of immediate data to a GPU memory buffer.
+ */
+void
+brw_store_data_imm32(struct brw_context *brw, drm_intel_bo *bo,
+ uint32_t offset, uint32_t imm)
+{
+ assert(brw->gen >= 6);
+
+ BEGIN_BATCH(4);
+ OUT_BATCH(MI_STORE_DATA_IMM | (4 - 2));
+ if (brw->gen >= 8)
+ OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ offset);
+ else {
+ OUT_BATCH(0); /* MBZ */
+ OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ offset);
+ }
+ OUT_BATCH(imm);
+ ADVANCE_BATCH();
+}
+
+/*
+ * Write 64-bits of immediate data to a GPU memory buffer.
+ */
+void
+brw_store_data_imm64(struct brw_context *brw, drm_intel_bo *bo,
+ uint32_t offset, uint64_t imm)
+{
+ assert(brw->gen >= 6);
+
+ BEGIN_BATCH(5);
+ OUT_BATCH(MI_STORE_DATA_IMM | (5 - 2));
+ if (brw->gen >= 8)
+ OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ offset);
+ else {
+ OUT_BATCH(0); /* MBZ */
+ OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ offset);
+ }
+ OUT_BATCH(imm & 0xffffffffu);
+ OUT_BATCH(imm >> 32);
+ ADVANCE_BATCH();
+}
diff --git a/src/mesa/drivers/dri/i965/brw_pipelined_register.h
b/src/mesa/drivers/dri/i965/brw_pipelined_register.h
new file mode 100644
index 0000000000..94d52433a1
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/brw_pipelined_register.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright © 2010-2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef BRW_PIPELINED_REGISTER_H
+#define BRW_PIPELINED_REGISTER_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void brw_load_register_mem32(struct brw_context *brw,
+ uint32_t reg,
+ drm_intel_bo *bo,
+ uint32_t offset);
+void brw_load_register_mem64(struct brw_context *brw,
+ uint32_t reg,
+ drm_intel_bo *bo,
+ uint32_t offset);
+
+void brw_store_register_mem32(struct brw_context *brw,
+ drm_intel_bo *bo,
+ uint32_t reg,
+ uint32_t offset);
+void brw_store_register_mem64(struct brw_context *brw,
+ drm_intel_bo *bo,
+ uint32_t reg,
+ uint32_t offset);
+
+void brw_load_register_imm32(struct brw_context *brw,
+ uint32_t reg,
+ uint32_t imm);
+void brw_load_register_imm64(struct brw_context *brw,
+ uint32_t reg,
+ uint64_t imm);
+
+void brw_load_register_reg(struct brw_context *brw,
+ uint32_t src,
+ uint32_t dest);
+void brw_load_register_reg64(struct brw_context *brw,
+ uint32_t src,
+ uint32_t dest);
+
+void brw_store_data_imm32(struct brw_context *brw,
+ drm_intel_bo *bo,
+ uint32_t offset,
+ uint32_t imm);
+void brw_store_data_imm64(struct brw_context *brw,
+ drm_intel_bo *bo,
+ uint32_t offset,
+ uint64_t imm);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BRW_PIPELINED_REGISTER_H */
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index ea58bf02cf..da1acd168a 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -41,6 +41,7 @@
#include "brw_gs.h"
#include "brw_wm.h"
#include "brw_cs.h"
+#include "brw_pipelined_register.h"
#include "main/framebuffer.h"
static const struct brw_tracked_state *gen4_atoms[] =
diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c
b/src/mesa/drivers/dri/i965/gen6_queryobj.c
index bbd3c44fb0..ce6813b531 100644
--- a/src/mesa/drivers/dri/i965/gen6_queryobj.c
+++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c
@@ -35,6 +35,7 @@
#include "brw_context.h"
#include "brw_defines.h"
+#include "brw_pipelined_register.h"
#include "brw_state.h"
#include "intel_batchbuffer.h"
#include "intel_buffer_objects.h"
diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c
b/src/mesa/drivers/dri/i965/gen7_l3_state.c
index dd68f036b3..f1cd3d8fd4 100644
--- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
@@ -26,6 +26,8 @@
#include "brw_context.h"
#include "brw_defines.h"
#include "brw_state.h"
+#include "brw_pipelined_register.h"
+
#include "intel_batchbuffer.h"
/**
diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c
b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index 17752742d4..df1f56a5a6 100644
--- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
@@ -31,6 +31,8 @@
#include "brw_context.h"
#include "brw_state.h"
#include "brw_defines.h"
+#include "brw_pipelined_register.h"
+
#include "intel_batchbuffer.h"
#include "intel_buffer_objects.h"
#include "main/transformfeedback.h"
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 71e5831cf1..080471594c 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -29,6 +29,7 @@
#include "brw_state.h"
#include "brw_defines.h"
#include "brw_wm.h"
+#include "brw_pipelined_register.h"
#include "main/framebuffer.h"
/**
diff --git a/src/mesa/drivers/dri/i965/hsw_queryobj.c
b/src/mesa/drivers/dri/i965/hsw_queryobj.c
index 0c558c5624..c3eeafc091 100644
--- a/src/mesa/drivers/dri/i965/hsw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/hsw_queryobj.c
@@ -30,6 +30,8 @@
#include "brw_context.h"
#include "brw_defines.h"
+#include "brw_pipelined_register.h"
+
#include "intel_batchbuffer.h"
#include "intel_buffer_objects.h"
diff --git a/src/mesa/drivers/dri/i965/hsw_sol.c
b/src/mesa/drivers/dri/i965/hsw_sol.c
index 32e70c9d55..d9c9539199 100644
--- a/src/mesa/drivers/dri/i965/hsw_sol.c
+++ b/src/mesa/drivers/dri/i965/hsw_sol.c
@@ -31,6 +31,8 @@
#include "brw_context.h"
#include "brw_state.h"
#include "brw_defines.h"
+#include "brw_pipelined_register.h"
+
#include "intel_batchbuffer.h"
#include "intel_buffer_objects.h"
#include "main/transformfeedback.h"
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 69b9c586d5..2a17babc13 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -488,227 +488,3 @@ intel_batchbuffer_data(struct brw_context *brw,
memcpy(brw->batch.map_next, data, bytes);
brw->batch.map_next += bytes >> 2;
}
-
-static void
-load_sized_register_mem(struct brw_context *brw,
- uint32_t reg,
- drm_intel_bo *bo,
- uint32_t offset,
- int size)
-{
- int i;
-
- /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
- assert(brw->gen >= 7);
-
- if (brw->gen >= 8) {
- BEGIN_BATCH(4 * size);
- for (i = 0; i < size; i++) {
- OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (4 - 2));
- OUT_BATCH(reg + i * 4);
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, offset + i * 4);
- }
- ADVANCE_BATCH();
- } else {
- BEGIN_BATCH(3 * size);
- for (i = 0; i < size; i++) {
- OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
- OUT_BATCH(reg + i * 4);
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, offset + i * 4);
- }
- ADVANCE_BATCH();
- }
-}
-
-void
-brw_load_register_mem32(struct brw_context *brw,
- uint32_t reg,
- drm_intel_bo *bo,
- uint32_t offset)
-{
- load_sized_register_mem(brw, reg, bo, offset, 1);
-}
-
-void
-brw_load_register_mem64(struct brw_context *brw,
- uint32_t reg,
- drm_intel_bo *bo,
- uint32_t offset)
-{
- load_sized_register_mem(brw, reg, bo, offset, 2);
-}
-
-/*
- * Write an arbitrary 32-bit register to a buffer via MI_STORE_REGISTER_MEM.
- */
-void
-brw_store_register_mem32(struct brw_context *brw,
- drm_intel_bo *bo, uint32_t reg, uint32_t offset)
-{
- assert(brw->gen >= 6);
-
- if (brw->gen >= 8) {
- BEGIN_BATCH(4);
- OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2));
- OUT_BATCH(reg);
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
- ADVANCE_BATCH();
- } else {
- BEGIN_BATCH(3);
- OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
- OUT_BATCH(reg);
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
- ADVANCE_BATCH();
- }
-}
-
-/*
- * Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM.
- */
-void
-brw_store_register_mem64(struct brw_context *brw,
- drm_intel_bo *bo, uint32_t reg, uint32_t offset)
-{
- assert(brw->gen >= 6);
-
- /* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to
- * read a full 64-bit register, we need to do two of them.
- */
- if (brw->gen >= 8) {
- BEGIN_BATCH(8);
- OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2));
- OUT_BATCH(reg);
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
- OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2));
- OUT_BATCH(reg + sizeof(uint32_t));
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset + sizeof(uint32_t));
- ADVANCE_BATCH();
- } else {
- BEGIN_BATCH(6);
- OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
- OUT_BATCH(reg);
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
- OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
- OUT_BATCH(reg + sizeof(uint32_t));
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset + sizeof(uint32_t));
- ADVANCE_BATCH();
- }
-}
-
-/*
- * Write a 32-bit register using immediate data.
- */
-void
-brw_load_register_imm32(struct brw_context *brw, uint32_t reg, uint32_t imm)
-{
- assert(brw->gen >= 6);
-
- BEGIN_BATCH(3);
- OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
- OUT_BATCH(reg);
- OUT_BATCH(imm);
- ADVANCE_BATCH();
-}
-
-/*
- * Write a 64-bit register using immediate data.
- */
-void
-brw_load_register_imm64(struct brw_context *brw, uint32_t reg, uint64_t imm)
-{
- assert(brw->gen >= 6);
-
- BEGIN_BATCH(5);
- OUT_BATCH(MI_LOAD_REGISTER_IMM | (5 - 2));
- OUT_BATCH(reg);
- OUT_BATCH(imm & 0xffffffff);
- OUT_BATCH(reg + 4);
- OUT_BATCH(imm >> 32);
- ADVANCE_BATCH();
-}
-
-/*
- * Copies a 32-bit register.
- */
-void
-brw_load_register_reg(struct brw_context *brw, uint32_t src, uint32_t dest)
-{
- assert(brw->gen >= 8 || brw->is_haswell);
-
- BEGIN_BATCH(3);
- OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2));
- OUT_BATCH(src);
- OUT_BATCH(dest);
- ADVANCE_BATCH();
-}
-
-/*
- * Copies a 64-bit register.
- */
-void
-brw_load_register_reg64(struct brw_context *brw, uint32_t src, uint32_t dest)
-{
- assert(brw->gen >= 8 || brw->is_haswell);
-
- BEGIN_BATCH(6);
- OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2));
- OUT_BATCH(src);
- OUT_BATCH(dest);
- OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2));
- OUT_BATCH(src + sizeof(uint32_t));
- OUT_BATCH(dest + sizeof(uint32_t));
- ADVANCE_BATCH();
-}
-
-/*
- * Write 32-bits of immediate data to a GPU memory buffer.
- */
-void
-brw_store_data_imm32(struct brw_context *brw, drm_intel_bo *bo,
- uint32_t offset, uint32_t imm)
-{
- assert(brw->gen >= 6);
-
- BEGIN_BATCH(4);
- OUT_BATCH(MI_STORE_DATA_IMM | (4 - 2));
- if (brw->gen >= 8)
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
- else {
- OUT_BATCH(0); /* MBZ */
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
- }
- OUT_BATCH(imm);
- ADVANCE_BATCH();
-}
-
-/*
- * Write 64-bits of immediate data to a GPU memory buffer.
- */
-void
-brw_store_data_imm64(struct brw_context *brw, drm_intel_bo *bo,
- uint32_t offset, uint64_t imm)
-{
- assert(brw->gen >= 6);
-
- BEGIN_BATCH(5);
- OUT_BATCH(MI_STORE_DATA_IMM | (5 - 2));
- if (brw->gen >= 8)
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
- else {
- OUT_BATCH(0); /* MBZ */
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
- }
- OUT_BATCH(imm & 0xffffffffu);
- OUT_BATCH(imm >> 32);
- ADVANCE_BATCH();
-}
--
2.11.0
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