From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeon/r600_pipe_common.h | 4 ----
src/gallium/drivers/radeon/r600_texture.c | 15 +++------------
2 files changed, 3 insertions(+), 16 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 7689054..d49f9d3 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -225,24 +225,20 @@ struct r600_fmask_info {
unsigned pitch_in_pixels;
unsigned bank_height;
unsigned slice_tile_max;
unsigned tile_mode_index;
};
struct r600_cmask_info {
uint64_t offset;
uint64_t size;
unsigned alignment;
- unsigned pitch;
- unsigned height;
- unsigned xalign;
- unsigned yalign;
unsigned slice_tile_max;
unsigned base_address_reg;
};
struct r600_texture {
struct r600_resource resource;
uint64_t size;
unsigned num_level0_transfers;
enum pipe_format db_render_format;
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index f79eae2..db65cd9 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -674,24 +674,20 @@ void r600_texture_get_cmask_info(struct
r600_common_screen *rscreen,
unsigned pitch_elements = align(rtex->resource.b.b.width0,
macro_tile_width);
unsigned height = align(rtex->resource.b.b.height0, macro_tile_height);
unsigned base_align = num_pipes * pipe_interleave_bytes;
unsigned slice_bytes =
((pitch_elements * height * element_bits + 7) / 8) /
cmask_tile_elements;
assert(macro_tile_width % 128 == 0);
assert(macro_tile_height % 128 == 0);
- out->pitch = pitch_elements;
- out->height = height;
- out->xalign = macro_tile_width;
- out->yalign = macro_tile_height;
out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
out->alignment = MAX2(256, base_align);
out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
align(slice_bytes, base_align);
}
static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
struct r600_texture *rtex,
struct r600_cmask_info *out)
{
@@ -723,24 +719,20 @@ static void si_texture_get_cmask_info(struct
r600_common_screen *rscreen,
unsigned base_align = num_pipes * pipe_interleave_bytes;
unsigned width = align(rtex->resource.b.b.width0, cl_width*8);
unsigned height = align(rtex->resource.b.b.height0, cl_height*8);
unsigned slice_elements = (width * height) / (8*8);
/* Each element of CMASK is a nibble. */
unsigned slice_bytes = slice_elements / 2;
- out->pitch = width;
- out->height = height;
- out->xalign = cl_width * 8;
- out->yalign = cl_height * 8;
out->slice_tile_max = (width * height) / (128*128);
if (out->slice_tile_max)
out->slice_tile_max -= 1;
out->alignment = MAX2(256, base_align);
out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
align(slice_bytes, base_align);
}
static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
@@ -924,25 +916,24 @@ void r600_print_texture_info(struct r600_texture *rtex,
FILE *f)
(rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
if (rtex->fmask.size)
fprintf(f, " FMask: offset=%"PRIu64", size=%"PRIu64",
alignment=%u, pitch_in_pixels=%u, "
"bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
rtex->fmask.offset, rtex->fmask.size,
rtex->fmask.alignment,
rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
rtex->fmask.slice_tile_max,
rtex->fmask.tile_mode_index);
if (rtex->cmask.size)
- fprintf(f, " CMask: offset=%"PRIu64", size=%"PRIu64",
alignment=%u, pitch=%u, "
- "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
+ fprintf(f, " CMask: offset=%"PRIu64", size=%"PRIu64",
alignment=%u, "
+ "slice_tile_max=%u\n",
rtex->cmask.offset, rtex->cmask.size,
rtex->cmask.alignment,
- rtex->cmask.pitch, rtex->cmask.height,
rtex->cmask.xalign,
- rtex->cmask.yalign, rtex->cmask.slice_tile_max);
+ rtex->cmask.slice_tile_max);
if (rtex->htile_buffer)
fprintf(f, " HTile: size=%u, alignment=%u, TC_compatible =
%u\n",
rtex->htile_buffer->b.b.width0,
rtex->htile_buffer->buf->alignment,
rtex->tc_compatible_htile);
if (rtex->dcc_offset) {
fprintf(f, " DCC: offset=%"PRIu64", size=%"PRIu64",
alignment=%u\n",
rtex->dcc_offset, rtex->surface.dcc_size,
--
2.7.4
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