From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeon/r600_texture.c | 4 +-
src/gallium/drivers/radeon/radeon_winsys.h | 62 +++++++++++-----------
src/gallium/winsys/radeon/drm/radeon_drm_surface.c | 4 +-
3 files changed, 36 insertions(+), 34 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index a89b285..c9c87c7 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -922,21 +922,21 @@ void r600_print_texture_info(struct r600_texture *rtex,
FILE *f)
fprintf(f, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
"blk_h=%u, array_size=%u, last_level=%u, "
"bpe=%u, nsamples=%u, flags=0x%x, %s\n",
rtex->resource.b.b.width0, rtex->resource.b.b.height0,
rtex->resource.b.b.depth0, rtex->surface.blk_w,
rtex->surface.blk_h,
rtex->resource.b.b.array_size, rtex->resource.b.b.last_level,
rtex->surface.bpe, rtex->resource.b.b.nr_samples,
rtex->surface.flags,
util_format_short_name(rtex->resource.b.b.format));
- fprintf(f, " Layout: size=%"PRIu64", alignment=%"PRIu64", bankw=%u, "
+ fprintf(f, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, "
"bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u,
scanout=%u\n",
rtex->surface.bo_size, rtex->surface.bo_alignment,
rtex->surface.bankw,
rtex->surface.bankh, rtex->surface.num_banks,
rtex->surface.mtilea,
rtex->surface.tile_split, rtex->surface.pipe_config,
(rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
if (rtex->fmask.size)
fprintf(f, " FMask: offset=%"PRIu64", size=%"PRIu64",
alignment=%u, pitch_in_pixels=%u, "
"bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
rtex->fmask.offset, rtex->fmask.size,
rtex->fmask.alignment,
@@ -952,21 +952,21 @@ void r600_print_texture_info(struct r600_texture *rtex,
FILE *f)
if (rtex->htile_buffer)
fprintf(f, " HTile: size=%u, alignment=%u, pitch=%u,
height=%u, "
"xalign=%u, yalign=%u, TC_compatible = %u\n",
rtex->htile_buffer->b.b.width0,
rtex->htile_buffer->buf->alignment, rtex->htile.pitch,
rtex->htile.height, rtex->htile.xalign,
rtex->htile.yalign,
rtex->tc_compatible_htile);
if (rtex->dcc_offset) {
- fprintf(f, " DCC: offset=%"PRIu64", size=%"PRIu64",
alignment=%"PRIu64"\n",
+ fprintf(f, " DCC: offset=%"PRIu64", size=%"PRIu64",
alignment=%u\n",
rtex->dcc_offset, rtex->surface.dcc_size,
rtex->surface.dcc_alignment);
for (i = 0; i <= rtex->resource.b.b.last_level; i++)
fprintf(f, " DCCLevel[%i]: enabled=%u,
offset=%"PRIu64", "
"fast_clear_size=%"PRIu64"\n",
i, rtex->surface.level[i].dcc_enabled,
rtex->surface.level[i].dcc_offset,
rtex->surface.level[i].dcc_fast_clear_size);
}
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
index 4b79752..4573efe 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -248,21 +248,21 @@ struct radeon_bo_metadata {
*/
uint32_t size_metadata;
uint32_t metadata[64];
};
enum radeon_feature_id {
RADEON_FID_R300_HYPERZ_ACCESS, /* ZMask + HiZ */
RADEON_FID_R300_CMASK_ACCESS,
};
-#define RADEON_SURF_MAX_LEVEL 32
+#define RADEON_SURF_MAX_LEVELS 15
enum radeon_surf_mode {
RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
RADEON_SURF_MODE_1D = 2,
RADEON_SURF_MODE_2D = 3,
};
/* the first 16 bits are reserved for libdrm_radeon, don't use them */
#define RADEON_SURF_SCANOUT (1 << 16)
#define RADEON_SURF_ZBUFFER (1 << 17)
@@ -271,74 +271,76 @@ enum radeon_surf_mode {
#define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
#define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
#define RADEON_SURF_FMASK (1 << 21)
#define RADEON_SURF_DISABLE_DCC (1 << 22)
#define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
#define RADEON_SURF_IMPORTED (1 << 24)
struct radeon_surf_level {
uint64_t offset;
uint64_t slice_size;
- uint32_t npix_x;
- uint32_t npix_y;
- uint32_t npix_z;
- uint32_t nblk_x;
- uint32_t nblk_y;
- uint32_t nblk_z;
- uint32_t pitch_bytes;
- enum radeon_surf_mode mode;
uint64_t dcc_offset;
uint64_t dcc_fast_clear_size;
+ uint16_t npix_x;
+ uint16_t npix_y;
+ uint16_t npix_z;
+ uint16_t nblk_x;
+ uint16_t nblk_y;
+ uint16_t nblk_z;
+ uint32_t pitch_bytes;
+ enum radeon_surf_mode mode;
bool dcc_enabled;
};
struct radeon_surf {
/* Format properties. */
- uint32_t blk_w;
- uint32_t blk_h;
- uint32_t bpe;
+ unsigned blk_w:4;
+ unsigned blk_h:4;
+ unsigned bpe:5;
uint32_t flags;
/* These are return values. Some of them can be set by the caller, but
* they will be treated as hints (e.g. bankw, bankh) and might be
* changed by the calculator.
*/
uint64_t bo_size;
- uint64_t bo_alignment;
+ uint32_t bo_alignment;
+
/* This applies to EG and later. */
- uint32_t bankw;
- uint32_t bankh;
- uint32_t mtilea;
- uint32_t tile_split;
- uint32_t stencil_tile_split;
- struct radeon_surf_level level[RADEON_SURF_MAX_LEVEL];
- struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVEL];
- uint32_t tiling_index[RADEON_SURF_MAX_LEVEL];
- uint32_t stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
- uint32_t pipe_config;
- uint32_t num_banks;
- uint32_t macro_tile_index;
- uint32_t micro_tile_mode; /* displayable, thin, depth,
rotated */
+ unsigned bankw:4; /* max 8 */
+ unsigned bankh:4; /* max 8 */
+ unsigned mtilea:4; /* max 8 */
+ unsigned tile_split:13; /* max 4K */
+ unsigned stencil_tile_split:13; /* max 4K */
+ unsigned pipe_config:5; /* max 17 */
+ unsigned num_banks:5; /* max 16 */
+ unsigned macro_tile_index:4; /* max 15 */
+ unsigned micro_tile_mode:3; /* displayable, thin,
depth, rotated */
/* Whether the depth miptree or stencil miptree as used by the DB are
* adjusted from their TC compatible form to ensure depth/stencil
* compatibility. If either is true, the corresponding plane cannot be
* sampled from.
*/
- bool depth_adjusted;
- bool stencil_adjusted;
+ unsigned depth_adjusted:1;
+ unsigned stencil_adjusted:1;
+
+ struct radeon_surf_level level[RADEON_SURF_MAX_LEVELS];
+ struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVELS];
+ uint8_t tiling_index[RADEON_SURF_MAX_LEVELS];
+ uint8_t stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
uint64_t dcc_size;
- uint64_t dcc_alignment;
+ uint32_t dcc_alignment;
/* TC-compatible HTILE only. */
uint64_t htile_size;
- uint64_t htile_alignment;
+ uint32_t htile_alignment;
};
struct radeon_bo_list_item {
uint64_t bo_size;
uint64_t vm_address;
uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
};
struct radeon_winsys {
/**
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
index fafcee1..18c68a5 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
@@ -154,21 +154,21 @@ static void surf_winsys_to_drm(struct radeon_surface
*surf_drm,
surf_drm->bo_size = surf_ws->bo_size;
surf_drm->bo_alignment = surf_ws->bo_alignment;
surf_drm->bankw = surf_ws->bankw;
surf_drm->bankh = surf_ws->bankh;
surf_drm->mtilea = surf_ws->mtilea;
surf_drm->tile_split = surf_ws->tile_split;
surf_drm->stencil_tile_split = surf_ws->stencil_tile_split;
- for (i = 0; i < RADEON_SURF_MAX_LEVEL; i++) {
+ for (i = 0; i < RADEON_SURF_MAX_LEVELS; i++) {
surf_level_winsys_to_drm(&surf_drm->level[i], &surf_ws->level[i]);
surf_level_winsys_to_drm(&surf_drm->stencil_level[i],
&surf_ws->stencil_level[i]);
surf_drm->tiling_index[i] = surf_ws->tiling_index[i];
surf_drm->stencil_tiling_index[i] = surf_ws->stencil_tiling_index[i];
}
}
static void surf_drm_to_winsys(struct radeon_drm_winsys *ws,
@@ -188,21 +188,21 @@ static void surf_drm_to_winsys(struct radeon_drm_winsys
*ws,
surf_ws->bo_alignment = surf_drm->bo_alignment;
surf_ws->bankw = surf_drm->bankw;
surf_ws->bankh = surf_drm->bankh;
surf_ws->mtilea = surf_drm->mtilea;
surf_ws->tile_split = surf_drm->tile_split;
surf_ws->stencil_tile_split = surf_drm->stencil_tile_split;
surf_ws->macro_tile_index = cik_get_macro_tile_index(surf_ws);
- for (i = 0; i < RADEON_SURF_MAX_LEVEL; i++) {
+ for (i = 0; i < RADEON_SURF_MAX_LEVELS; i++) {
surf_level_drm_to_winsys(&surf_ws->level[i], &surf_drm->level[i]);
surf_level_drm_to_winsys(&surf_ws->stencil_level[i],
&surf_drm->stencil_level[i]);
surf_ws->tiling_index[i] = surf_drm->tiling_index[i];
surf_ws->stencil_tiling_index[i] = surf_drm->stencil_tiling_index[i];
}
set_micro_tile_mode(surf_ws, &ws->info);
}
--
2.7.4
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