From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeon/r600_pipe_common.h | 9 -----
src/gallium/drivers/radeon/r600_texture.c | 49 ++++++++++++---------------
src/gallium/drivers/radeon/radeon_winsys.h | 1 -
3 files changed, 21 insertions(+), 38 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 1700371..7689054 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -233,28 +233,20 @@ struct r600_cmask_info {
uint64_t size;
unsigned alignment;
unsigned pitch;
unsigned height;
unsigned xalign;
unsigned yalign;
unsigned slice_tile_max;
unsigned base_address_reg;
};
-struct r600_htile_info {
- unsigned pitch;
- unsigned height;
- unsigned xalign;
- unsigned yalign;
- unsigned alignment;
-};
-
struct r600_texture {
struct r600_resource resource;
uint64_t size;
unsigned num_level0_transfers;
enum pipe_format db_render_format;
bool is_depth;
bool db_compatible;
bool can_sample_z;
bool can_sample_s;
@@ -266,21 +258,20 @@ struct r600_texture {
/* Colorbuffer compression and fast clear. */
struct r600_fmask_info fmask;
struct r600_cmask_info cmask;
struct r600_resource *cmask_buffer;
uint64_t dcc_offset; /* 0 = disabled */
unsigned cb_color_info; /* fast clear enable bit
*/
unsigned color_clear_value[2];
unsigned last_msaa_resolve_target_micro_mode;
/* Depth buffer compression and fast clear. */
- struct r600_htile_info htile;
struct r600_resource *htile_buffer;
bool tc_compatible_htile;
bool depth_cleared; /* if it was cleared at
least once */
float depth_clear_value;
bool stencil_cleared; /* if it was cleared
at least once */
uint8_t stencil_clear_value;
bool non_disp_tiling; /* R600-Cayman only */
/* Whether the texture is a displayable back buffer and needs DCC
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index 74977ea..4d4be97 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -796,42 +796,44 @@ static void r600_texture_alloc_cmask_separate(struct
r600_common_screen *rscreen
rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
if (rscreen->chip_class >= SI)
rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
else
rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
p_atomic_inc(&rscreen->compressed_colortex_counter);
}
-static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
- struct r600_texture *rtex)
+static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
+ struct r600_texture *rtex)
{
unsigned cl_width, cl_height, width, height;
unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
unsigned num_pipes = rscreen->info.num_tile_pipes;
+ rtex->surface.htile_size = 0;
+
if (rscreen->chip_class <= EVERGREEN &&
rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
- return 0;
+ return;
/* HW bug on R6xx. */
if (rscreen->chip_class == R600 &&
(rtex->resource.b.b.width0 > 7680 ||
rtex->resource.b.b.height0 > 7680))
- return 0;
+ return;
/* HTILE is broken with 1D tiling on old kernels and CIK. */
if (rscreen->chip_class >= CIK &&
rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
- return 0;
+ return;
/* Overalign HTILE on P2 configs to work around GPU hangs in
* piglit/depthstencil-render-miplevels 585.
*
* This has been confirmed to help Kabini & Stoney, where the hangs
* are always reproducible. I think I have seen the test hang
* on Carrizo too, though it was very rare there.
*/
if (rscreen->chip_class >= CIK && num_pipes < 4)
num_pipes = 4;
@@ -852,73 +854,66 @@ static unsigned r600_texture_get_htile_size(struct
r600_common_screen *rscreen,
case 8:
cl_width = 64;
cl_height = 64;
break;
case 16:
cl_width = 128;
cl_height = 64;
break;
default:
assert(0);
- return 0;
+ return;
}
width = align(rtex->resource.b.b.width0, cl_width * 8);
height = align(rtex->resource.b.b.height0, cl_height * 8);
slice_elements = (width * height) / (8 * 8);
slice_bytes = slice_elements * 4;
pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
base_align = num_pipes * pipe_interleave_bytes;
- rtex->htile.pitch = width;
- rtex->htile.height = height;
- rtex->htile.xalign = cl_width * 8;
- rtex->htile.yalign = cl_height * 8;
- rtex->htile.alignment = base_align;
-
- return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
+ rtex->surface.htile_alignment = base_align;
+ rtex->surface.htile_size =
+ (util_max_layer(&rtex->resource.b.b, 0) + 1) *
align(slice_bytes, base_align);
}
static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
struct r600_texture *rtex)
{
- uint64_t htile_size, alignment;
uint32_t clear_value;
if (rtex->tc_compatible_htile) {
- htile_size = rtex->surface.htile_size;
- alignment = rtex->surface.htile_alignment;
clear_value = 0x0000030F;
} else {
- htile_size = r600_texture_get_htile_size(rscreen, rtex);
- alignment = rtex->htile.alignment;
+ r600_texture_get_htile_size(rscreen, rtex);
clear_value = 0;
}
- if (!htile_size)
+ if (!rtex->surface.htile_size)
return;
rtex->htile_buffer = (struct r600_resource*)
- r600_aligned_buffer_create(&rscreen->b,
PIPE_BIND_CUSTOM,
- PIPE_USAGE_DEFAULT,
- htile_size, alignment);
+ r600_aligned_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
+ PIPE_USAGE_DEFAULT,
+ rtex->surface.htile_size,
+ rtex->surface.htile_alignment);
if (rtex->htile_buffer == NULL) {
/* this is not a fatal error as we can still keep rendering
* without htile buffer */
R600_ERR("Failed to create buffer object for htile buffer.\n");
} else {
r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b,
- 0, htile_size, clear_value,
- R600_COHERENCY_NONE);
+ 0, rtex->surface.htile_size,
+ clear_value, R600_COHERENCY_NONE);
}
}
void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
{
int i;
fprintf(f, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
"blk_h=%u, array_size=%u, last_level=%u, "
"bpe=%u, nsamples=%u, flags=0x%x, %s\n",
@@ -944,25 +939,23 @@ void r600_print_texture_info(struct r600_texture *rtex,
FILE *f)
rtex->fmask.slice_tile_max,
rtex->fmask.tile_mode_index);
if (rtex->cmask.size)
fprintf(f, " CMask: offset=%"PRIu64", size=%"PRIu64",
alignment=%u, pitch=%u, "
"height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
rtex->cmask.offset, rtex->cmask.size,
rtex->cmask.alignment,
rtex->cmask.pitch, rtex->cmask.height,
rtex->cmask.xalign,
rtex->cmask.yalign, rtex->cmask.slice_tile_max);
if (rtex->htile_buffer)
- fprintf(f, " HTile: size=%u, alignment=%u, pitch=%u,
height=%u, "
- "xalign=%u, yalign=%u, TC_compatible = %u\n",
+ fprintf(f, " HTile: size=%u, alignment=%u, TC_compatible =
%u\n",
rtex->htile_buffer->b.b.width0,
- rtex->htile_buffer->buf->alignment, rtex->htile.pitch,
- rtex->htile.height, rtex->htile.xalign,
rtex->htile.yalign,
+ rtex->htile_buffer->buf->alignment,
rtex->tc_compatible_htile);
if (rtex->dcc_offset) {
fprintf(f, " DCC: offset=%"PRIu64", size=%"PRIu64",
alignment=%u\n",
rtex->dcc_offset, rtex->surface.dcc_size,
rtex->surface.dcc_alignment);
for (i = 0; i <= rtex->resource.b.b.last_level; i++)
fprintf(f, " DCCLevel[%i]: enabled=%u,
offset=%"PRIu64", "
"fast_clear_size=%"PRIu64"\n",
i, rtex->surface.level[i].dcc_enabled,
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
index a28bac1..bf4bb82 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -320,21 +320,20 @@ struct radeon_surf {
unsigned depth_adjusted:1;
unsigned stencil_adjusted:1;
struct radeon_surf_level level[RADEON_SURF_MAX_LEVELS];
struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVELS];
uint8_t tiling_index[RADEON_SURF_MAX_LEVELS];
uint8_t stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
uint64_t dcc_size;
uint32_t dcc_alignment;
- /* TC-compatible HTILE only. */
uint64_t htile_size;
uint32_t htile_alignment;
};
struct radeon_bo_list_item {
uint64_t bo_size;
uint64_t vm_address;
uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
};
--
2.7.4
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