From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeon/r600_texture.c | 6 ++----
src/gallium/drivers/radeon/radeon_winsys.h | 10 +--------
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 7 -------
src/gallium/winsys/radeon/drm/radeon_drm_surface.c | 24 ++++++----------------
4 files changed, 9 insertions(+), 38 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index 27035c0..c386549 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -1289,24 +1289,21 @@ struct pipe_resource *r600_texture_create(struct
pipe_screen *screen,
util_format_is_depth_or_stencil(templ->format);
int r;
r = r600_init_surface(rscreen, &surface, templ,
r600_choose_tiling(rscreen, templ),
is_flushed_depth, tc_compatible_htile);
if (r) {
return NULL;
}
- r = rscreen->ws->surface_best(rscreen->ws, &surface);
- if (r) {
- return NULL;
- }
+
return (struct pipe_resource *)r600_texture_create_object(screen,
templ, 0,
0, NULL,
&surface);
}
static struct pipe_resource *r600_texture_from_handle(struct pipe_screen
*screen,
const struct
pipe_resource *templ,
struct winsys_handle
*whandle,
unsigned usage)
{
struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
@@ -1342,20 +1339,21 @@ static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen *screen
array_mode = RADEON_SURF_MODE_1D;
else
array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
r = r600_init_surface(rscreen, &surface, templ, array_mode,
false, false);
if (r) {
return NULL;
}
+ surface.flags |= RADEON_SURF_IMPORTED;
if (metadata.scanout)
surface.flags |= RADEON_SURF_SCANOUT;
rtex = r600_texture_create_object(screen, templ, stride,
offset, buf, &surface);
if (!rtex)
return NULL;
rtex->resource.is_shared = true;
rtex->resource.external_usage = usage;
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
index 8946209..75badd0 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -272,20 +272,21 @@ enum radeon_feature_id {
#define RADEON_SURF_MODE_2D 3
#define RADEON_SURF_SCANOUT (1 << 16)
#define RADEON_SURF_ZBUFFER (1 << 17)
#define RADEON_SURF_SBUFFER (1 << 18)
#define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER |
RADEON_SURF_SBUFFER)
#define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
#define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
#define RADEON_SURF_FMASK (1 << 21)
#define RADEON_SURF_DISABLE_DCC (1 << 22)
#define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
+#define RADEON_SURF_IMPORTED (1 << 24)
#define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT)
& RADEON_SURF_ ## field ## _MASK)
#define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) <<
RADEON_SURF_ ## field ## _SHIFT)
#define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK <<
RADEON_SURF_ ## field ## _SHIFT))
struct radeon_surf_level {
uint64_t offset;
uint64_t slice_size;
uint32_t npix_x;
uint32_t npix_y;
@@ -737,29 +738,20 @@ struct radeon_winsys {
/**
* Initialize surface
*
* \param ws The winsys this function is called from.
* \param surf Surface structure ptr
*/
int (*surface_init)(struct radeon_winsys *ws,
struct radeon_surf *surf);
- /**
- * Find best values for a surface
- *
- * \param ws The winsys this function is called from.
- * \param surf Surface structure ptr
- */
- int (*surface_best)(struct radeon_winsys *ws,
- struct radeon_surf *surf);
-
uint64_t (*query_value)(struct radeon_winsys *ws,
enum radeon_value_id value);
bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
unsigned num_registers, uint32_t *out);
};
static inline bool radeon_emitted(struct radeon_winsys_cs *cs, unsigned num_dw)
{
return cs && (cs->prev_dw + cs->current.cdw > num_dw);
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index c5462bc..95da4ac 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -570,21 +570,14 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
/* Make sure HTILE covers the whole miptree, because the shader reads
* TC-compatible HTILE even for levels where it's disabled by DB.
*/
if (surf->htile_size && surf->last_level)
surf->htile_size *= 2;
return 0;
}
-static int amdgpu_surface_best(struct radeon_winsys *rws,
- struct radeon_surf *surf)
-{
- return 0;
-}
-
void amdgpu_surface_init_functions(struct amdgpu_winsys *ws)
{
ws->base.surface_init = amdgpu_surface_init;
- ws->base.surface_best = amdgpu_surface_best;
}
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
index 0399e5a..8a88ee5 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
@@ -179,40 +179,28 @@ static void surf_drm_to_winsys(struct radeon_drm_winsys
*ws,
static int radeon_winsys_surface_init(struct radeon_winsys *rws,
struct radeon_surf *surf_ws)
{
struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
struct radeon_surface surf_drm;
int r;
surf_winsys_to_drm(&surf_drm, surf_ws);
- r = radeon_surface_init(ws->surf_man, &surf_drm);
- if (r)
- return r;
-
- surf_drm_to_winsys(ws, surf_ws, &surf_drm);
- return 0;
-}
-
-static int radeon_winsys_surface_best(struct radeon_winsys *rws,
- struct radeon_surf *surf_ws)
-{
- struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
- struct radeon_surface surf_drm;
- int r;
-
- surf_winsys_to_drm(&surf_drm, surf_ws);
+ if (!(surf_ws->flags & RADEON_SURF_IMPORTED)) {
+ r = radeon_surface_best(ws->surf_man, &surf_drm);
+ if (r)
+ return r;
+ }
- r = radeon_surface_best(ws->surf_man, &surf_drm);
+ r = radeon_surface_init(ws->surf_man, &surf_drm);
if (r)
return r;
surf_drm_to_winsys(ws, surf_ws, &surf_drm);
return 0;
}
void radeon_surface_init_functions(struct radeon_drm_winsys *ws)
{
ws->base.surface_init = radeon_winsys_surface_init;
- ws->base.surface_best = radeon_winsys_surface_best;
}
--
2.7.4
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