From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeon/r600_texture.c | 62 ++++++++++++-------------------
1 file changed, 24 insertions(+), 38 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index c386549..1b1ea66 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -185,26 +185,31 @@ static unsigned r600_texture_get_offset(struct
r600_texture *rtex, unsigned leve
return rtex->surface.level[level].offset +
box->z * rtex->surface.level[level].slice_size +
box->y / util_format_get_blockheight(format) *
rtex->surface.level[level].pitch_bytes +
box->x / util_format_get_blockwidth(format) *
util_format_get_blocksize(format);
}
static int r600_init_surface(struct r600_common_screen *rscreen,
struct radeon_surf *surface,
const struct pipe_resource *ptex,
unsigned array_mode,
+ unsigned pitch_in_bytes_override,
+ unsigned offset,
+ bool is_imported,
+ bool is_scanout,
bool is_flushed_depth,
bool tc_compatible_htile)
{
const struct util_format_description *desc =
util_format_description(ptex->format);
bool is_depth, is_stencil;
+ int r, i;
is_depth = util_format_has_depth(desc);
is_stencil = util_format_has_stencil(desc);
surface->npix_x = ptex->width0;
surface->npix_y = ptex->height0;
surface->npix_z = ptex->depth0;
surface->blk_w = util_format_get_blockwidth(ptex->format);
surface->blk_h = util_format_get_blockheight(ptex->format);
surface->blk_d = 1;
@@ -275,61 +280,51 @@ static int r600_init_surface(struct r600_common_screen
*rscreen,
if (rscreen->chip_class >= SI) {
surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
}
if (rscreen->chip_class >= VI &&
(ptex->flags & R600_RESOURCE_FLAG_DISABLE_DCC ||
ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT))
surface->flags |= RADEON_SURF_DISABLE_DCC;
- if (ptex->bind & PIPE_BIND_SCANOUT) {
+ if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
/* This should catch bugs in gallium users setting incorrect
flags. */
assert(surface->nsamples == 1 &&
surface->array_size == 1 &&
surface->npix_z == 1 &&
surface->last_level == 0 &&
!(surface->flags & RADEON_SURF_Z_OR_SBUFFER));
surface->flags |= RADEON_SURF_SCANOUT;
}
- return 0;
-}
-static int r600_setup_surface(struct pipe_screen *screen,
- struct r600_texture *rtex,
- unsigned pitch_in_bytes_override,
- unsigned offset)
-{
- struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
- unsigned i;
- int r;
+ if (is_imported)
+ surface->flags |= RADEON_SURF_IMPORTED;
- r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
+ r = rscreen->ws->surface_init(rscreen->ws, surface);
if (r) {
return r;
}
- rtex->size = rtex->surface.bo_size;
-
- if (pitch_in_bytes_override && pitch_in_bytes_override !=
rtex->surface.level[0].pitch_bytes) {
+ if (pitch_in_bytes_override && pitch_in_bytes_override !=
surface->level[0].pitch_bytes) {
/* old ddx on evergreen over estimate alignment for 1d, only 1
level
* for those
*/
- rtex->surface.level[0].nblk_x = pitch_in_bytes_override /
rtex->surface.bpe;
- rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
- rtex->surface.level[0].slice_size = pitch_in_bytes_override *
rtex->surface.level[0].nblk_y;
+ surface->level[0].nblk_x = pitch_in_bytes_override /
surface->bpe;
+ surface->level[0].pitch_bytes = pitch_in_bytes_override;
+ surface->level[0].slice_size = pitch_in_bytes_override *
surface->level[0].nblk_y;
}
if (offset) {
- for (i = 0; i < ARRAY_SIZE(rtex->surface.level); ++i)
- rtex->surface.level[i].offset += offset;
+ for (i = 0; i < ARRAY_SIZE(surface->level); ++i)
+ surface->level[i].offset += offset;
}
return 0;
}
static void r600_texture_init_metadata(struct r600_texture *rtex,
struct radeon_bo_metadata *metadata)
{
struct radeon_surf *surface = &rtex->surface;
memset(metadata, 0, sizeof(*metadata));
@@ -1046,22 +1041,20 @@ void r600_print_texture_info(struct r600_texture *rtex,
FILE *f)
rtex->surface.stencil_level[i].pitch_bytes,
rtex->surface.stencil_level[i].mode);
}
}
}
/* Common processing for r600_texture_create and r600_texture_from_handle */
static struct r600_texture *
r600_texture_create_object(struct pipe_screen *screen,
const struct pipe_resource *base,
- unsigned pitch_in_bytes_override,
- unsigned offset,
struct pb_buffer *buf,
struct radeon_surf *surface)
{
struct r600_texture *rtex;
struct r600_resource *resource;
struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
rtex = CALLOC_STRUCT(r600_texture);
if (!rtex)
return NULL;
@@ -1070,24 +1063,21 @@ r600_texture_create_object(struct pipe_screen *screen,
resource->b.b = *base;
resource->b.b.next = NULL;
resource->b.vtbl = &r600_texture_vtbl;
pipe_reference_init(&resource->b.b.reference, 1);
resource->b.b.screen = screen;
/* don't include stencil-only formats which we don't support for
rendering */
rtex->is_depth =
util_format_has_depth(util_format_description(rtex->resource.b.b.format));
rtex->surface = *surface;
- if (r600_setup_surface(screen, rtex, pitch_in_bytes_override, offset)) {
- FREE(rtex);
- return NULL;
- }
+ rtex->size = rtex->surface.bo_size;
rtex->tc_compatible_htile = rtex->surface.htile_size != 0;
assert(!!(rtex->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE) ==
rtex->tc_compatible_htile);
/* TC-compatible HTILE only supports Z32_FLOAT. */
if (rtex->tc_compatible_htile)
rtex->db_render_format = PIPE_FORMAT_Z32_FLOAT;
else
rtex->db_render_format = base->format;
@@ -1284,28 +1274,29 @@ struct pipe_resource *r600_texture_create(struct
pipe_screen *screen,
rscreen->chip_class >= VI &&
(templ->flags & PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY) &&
!(rscreen->debug_flags & DBG_NO_HYPERZ) &&
!is_flushed_depth &&
templ->nr_samples <= 1 && /* TC-compat HTILE is less efficient
with MSAA */
util_format_is_depth_or_stencil(templ->format);
int r;
r = r600_init_surface(rscreen, &surface, templ,
- r600_choose_tiling(rscreen, templ),
- is_flushed_depth, tc_compatible_htile);
+ r600_choose_tiling(rscreen, templ), 0, 0,
+ false, false, is_flushed_depth,
+ tc_compatible_htile);
if (r) {
return NULL;
}
- return (struct pipe_resource *)r600_texture_create_object(screen,
templ, 0,
- 0, NULL,
&surface);
+ return (struct pipe_resource *)
+ r600_texture_create_object(screen, templ, NULL, &surface);
}
static struct pipe_resource *r600_texture_from_handle(struct pipe_screen
*screen,
const struct
pipe_resource *templ,
struct winsys_handle
*whandle,
unsigned usage)
{
struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
struct pb_buffer *buf = NULL;
unsigned stride = 0, offset = 0;
@@ -1333,32 +1324,27 @@ static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen *screen
surface.mtilea = metadata.mtilea;
surface.num_banks = metadata.num_banks;
if (metadata.macrotile == RADEON_LAYOUT_TILED)
array_mode = RADEON_SURF_MODE_2D;
else if (metadata.microtile == RADEON_LAYOUT_TILED)
array_mode = RADEON_SURF_MODE_1D;
else
array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
- r = r600_init_surface(rscreen, &surface, templ, array_mode,
- false, false);
+ r = r600_init_surface(rscreen, &surface, templ, array_mode, stride,
+ offset, true, metadata.scanout, false, false);
if (r) {
return NULL;
}
- surface.flags |= RADEON_SURF_IMPORTED;
- if (metadata.scanout)
- surface.flags |= RADEON_SURF_SCANOUT;
-
- rtex = r600_texture_create_object(screen, templ, stride,
- offset, buf, &surface);
+ rtex = r600_texture_create_object(screen, templ, buf, &surface);
if (!rtex)
return NULL;
rtex->resource.is_shared = true;
rtex->resource.external_usage = usage;
if (rscreen->apply_opaque_metadata)
rscreen->apply_opaque_metadata(rscreen, rtex, &metadata);
return &rtex->resource.b.b;
--
2.7.4
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