Ping? I believe all the concerns about this patchset (and the DRM patch to add KBL) have been addressed. Can someone push this to master? Shall I rebase and resend the patches?
Sarah Sharp On Tue, Nov 17, 2015 at 11:40:53AM -0800, Sarah Sharp wrote: > Add PCI IDs for the Intel Kabylake platforms. The IDs are taken > directly from the Linux kernel patches, which are under review: > > http://lists.freedesktop.org/archives/intel-gfx/2015-October/078967.html > http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=kbl-upstream-v2 > > The Kabylake PCI IDs taken from the kernel are rearranged to be in order > of GT type, then PCI ID. > > Please note that if this patch is backported, the following fixes will > need to be added before this patch: > > commit 28ed1e08e8ba98e "i965/skl: Remove early platform support" > commit c1e38ad37042b0e "i965/skl: Use larger URB size where available." > > Thanks to Ben for fixing a bug around setting urb.size, and being > patient with my questions about what the various fields mean. > > Signed-off-by: Sarah Sharp <sarah.a.sh...@linux.intel.com> > Suggested-by: Ben Widawsky <benjamin.widaw...@intel.com> > Tested-by: Rodrigo Vivi <rodrigo.v...@intel.com> (KBL-GT2) > --- > > v2: > - reorder the PCI IDs > - rebase on latest mesa master > > include/pci_ids/i965_pci_ids.h | 22 +++++++++++ > src/mesa/drivers/dri/i965/brw_device_info.c | 60 > +++++++++++++++++++++++++++++ > 2 files changed, 82 insertions(+) > > diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h > index 5891ba6..5139e27 100644 > --- a/include/pci_ids/i965_pci_ids.h > +++ b/include/pci_ids/i965_pci_ids.h > @@ -132,6 +132,28 @@ CHIPSET(0x1932, skl_gt4, "Intel(R) Skylake GT4") > CHIPSET(0x193A, skl_gt4, "Intel(R) Skylake GT4") > CHIPSET(0x193B, skl_gt4, "Intel(R) Skylake GT4") > CHIPSET(0x193D, skl_gt4, "Intel(R) Skylake GT4") > +CHIPSET(0x5902, kbl_gt1, "Intel(R) Kabylake GT1") > +CHIPSET(0x5906, kbl_gt1, "Intel(R) Kabylake GT1") > +CHIPSET(0x590A, kbl_gt1, "Intel(R) Kabylake GT1") > +CHIPSET(0x590B, kbl_gt1, "Intel(R) Kabylake GT1") > +CHIPSET(0x590E, kbl_gt1, "Intel(R) Kabylake GT1") > +CHIPSET(0x5913, kbl_gt1_5, "Intel(R) Kabylake GT1.5") > +CHIPSET(0x5915, kbl_gt1_5, "Intel(R) Kabylake GT1.5") > +CHIPSET(0x5917, kbl_gt1_5, "Intel(R) Kabylake GT1.5") > +CHIPSET(0x5912, kbl_gt2, "Intel(R) Kabylake GT2") > +CHIPSET(0x5916, kbl_gt2, "Intel(R) Kabylake GT2") > +CHIPSET(0x591A, kbl_gt2, "Intel(R) Kabylake GT2") > +CHIPSET(0x591B, kbl_gt2, "Intel(R) Kabylake GT2") > +CHIPSET(0x591D, kbl_gt2, "Intel(R) Kabylake GT2") > +CHIPSET(0x591E, kbl_gt2, "Intel(R) Kabylake GT2") > +CHIPSET(0x5921, kbl_gt2, "Intel(R) Kabylake GT2F") > +CHIPSET(0x5926, kbl_gt3, "Intel(R) Kabylake GT3") > +CHIPSET(0x592A, kbl_gt3, "Intel(R) Kabylake GT3") > +CHIPSET(0x592B, kbl_gt3, "Intel(R) Kabylake GT3") > +CHIPSET(0x5932, kbl_gt4, "Intel(R) Kabylake GT4") > +CHIPSET(0x593A, kbl_gt4, "Intel(R) Kabylake GT4") > +CHIPSET(0x593B, kbl_gt4, "Intel(R) Kabylake GT4") > +CHIPSET(0x593D, kbl_gt4, "Intel(R) Kabylake GT4") > CHIPSET(0x22B0, chv, "Intel(R) HD Graphics (Cherryview)") > CHIPSET(0x22B1, chv, "Intel(R) HD Graphics (Cherryview)") > CHIPSET(0x22B2, chv, "Intel(R) HD Graphics (Cherryview)") > diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c > b/src/mesa/drivers/dri/i965/brw_device_info.c > index 4550550..c58e4a5 100644 > --- a/src/mesa/drivers/dri/i965/brw_device_info.c > +++ b/src/mesa/drivers/dri/i965/brw_device_info.c > @@ -371,6 +371,66 @@ static const struct brw_device_info brw_device_info_bxt > = { > } > }; > > +/* > + * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+. > + * There's no KBL entry. Using the default SKL (GEN9) GS entries value. > + */ > + > +/* > + * Both SKL and KBL support a maximum of 64 threads per > + * Pixel Shader Dispatch (PSD) unit. > + */ > +#define KBL_MAX_THREADS_PER_PSD 64 > + > +static const struct brw_device_info brw_device_info_kbl_gt1 = { > + GEN9_FEATURES, > + .gt = 1, > + > + .max_cs_threads = 7 * 6, > + .max_wm_threads = KBL_MAX_THREADS_PER_PSD * 2, > + .urb.size = 192, > +}; > + > +static const struct brw_device_info brw_device_info_kbl_gt1_5 = { > + GEN9_FEATURES, > + .gt = 1, > + > + .max_cs_threads = 7 * 6, > + .max_wm_threads = KBL_MAX_THREADS_PER_PSD * 3, > +}; > + > +static const struct brw_device_info brw_device_info_kbl_gt2 = { > + GEN9_FEATURES, > + .gt = 2, > + > + .max_wm_threads = KBL_MAX_THREADS_PER_PSD * 3, > +}; > + > +static const struct brw_device_info brw_device_info_kbl_gt3 = { > + GEN9_FEATURES, > + .gt = 3, > + > + .max_wm_threads = KBL_MAX_THREADS_PER_PSD * 6, > +}; > + > +static const struct brw_device_info brw_device_info_kbl_gt4 = { > + GEN9_FEATURES, > + .gt = 4, > + > + .max_wm_threads = KBL_MAX_THREADS_PER_PSD * 9, > + /* > + * From the "L3 Allocation and Programming" documentation: > + * > + * "URB is limited to 1008KB due to programming restrictions. This > + * is not a restriction of the L3 implementation, but of the FF and > + * other clients. Therefore, in a GT4 implementation it is > + * possible for the programmed allocation of the L3 data array to > + * provide 3*384KB=1152KB for URB, but only 1008KB of this > + * will be used." > + */ > + .urb.size = 1008 / 3, > +}; > + > const struct brw_device_info * > brw_get_device_info(int devid) > { > -- > 2.3.0 > > _______________________________________________ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/mesa-dev _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
