On 06/17/2013 07:28:07 PM, Scott Wood wrote:
On 06/17/2013 12:07:41 AM, Lian Minghuan-b31939 wrote:
+ compatible = "fsl,mpic-msi";
+ reg = <0x41600 0x200 0x44140 4>;
Why 0x200?
[Minghuan] The offsets of the MSIA registers are from 0x41600 to
0x417ff, and the size is 0x200.
offset 0x41600-0x4170 are MSIIRA1-7.
0x41720 is MSISRA,
0x41750 is MSIIR.
The others are reserved.
There is no MSIIRA on fsl,mpic-msi.
Sigh, I was thinking of MSIIR1A -- which of course is distinct from
both MSIIRA1 and MSIIRA. :-P
So it's just a bug that pq3-mpic.dtsi has a length of 0x80?
-Scott
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