Hello Mani, Sorry for the delayed reply. I just came back from vacation.
On Thu, Jul 24, 2025 at 11:00:05AM +0530, Manivannan Sadhasivam wrote: > On Fri, Jul 18, 2025 at 12:39:50PM GMT, Niklas Cassel wrote: > > On Fri, Jul 18, 2025 at 12:28:44PM +0200, Niklas Cassel wrote: > > > On Tue, Jul 15, 2025 at 07:51:03PM +0530, Manivannan Sadhasivam via B4 > > > Relay wrote: > > > 2) Testing link down reset: > > > > > > selftests before link down reset: > > > # FAILED: 14 / 16 tests passed. > > > > > > ## On EP side: > > > # echo 0 > /sys/kernel/config/pci_ep/controllers/a40000000.pcie-ep/start > > > && \ > > > sleep 0.1 && echo 1 > > > > /sys/kernel/config/pci_ep/controllers/a40000000.pcie-ep/start > > > > > > > > > [ 111.137162] rockchip-dw-pcie a40000000.pcie: > > > PCIE_CLIENT_INTR_STATUS_MISC: 0x4 > > > [ 111.137881] rockchip-dw-pcie a40000000.pcie: LTSSM_STATUS: 0x0 > > > [ 111.138432] rockchip-dw-pcie a40000000.pcie: hot reset or link-down > > > reset > > > [ 111.139067] pcieport 0000:00:00.0: Recovering Root Port due to Link > > > Down > > > [ 111.139686] pci-endpoint-test 0000:01:00.0: AER: can't recover (no > > > error_detected callback) > > > [ 111.255407] rockchip-dw-pcie a40000000.pcie: PCIe Gen.3 x4 link up > > > [ 111.256019] rockchip-dw-pcie a40000000.pcie: Root Port reset completed > > > [ 111.383401] pcieport 0000:00:00.0: Root Port has been reset > > > [ 111.384060] pcieport 0000:00:00.0: AER: device recovery failed > > > [ 111.384582] rockchip-dw-pcie a40000000.pcie: > > > PCIE_CLIENT_INTR_STATUS_MISC: 0x3 > > > [ 111.385218] rockchip-dw-pcie a40000000.pcie: LTSSM_STATUS: 0x230011 > > > [ 111.385771] rockchip-dw-pcie a40000000.pcie: Received Link up event. > > > Starting enumeration! > > > [ 111.390866] pcieport 0000:00:00.0: bridge configuration invalid ([bus > > > 00-00]), reconfiguring > > > [ 111.391650] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01 > > > > > > Basically all tests timeout > > > # FAILED: 1 / 16 tests passed. > > > > > > Which is the same as before this patch series. > > > > The above was with CONFIG_PCIEAER=y > > > > This is kind of expected since the pci_endpoint_test driver doesn't have the > AER > err_handlers defined. I see. Would be nice if we could add them then, so that we can verify that this series is working as intended. > > > Wilfred suggested that I tried without this config set. > > > > However, doing so, I got the exact same result: > > # FAILED: 1 / 16 tests passed. > > > > Interesting. Could you please share the dmesg log like above. It is looking exactly like the dmesg above [ 86.820059] rockchip-dw-pcie a40000000.pcie: PCIE_CLIENT_INTR_STATUS_MISC: 0x4 [ 86.820791] rockchip-dw-pcie a40000000.pcie: LTSSM_STATUS: 0x0 [ 86.821344] rockchip-dw-pcie a40000000.pcie: hot reset or link-down reset [ 86.821978] pcieport 0000:00:00.0: Recovering Root Port due to Link Down [ 87.040551] rockchip-dw-pcie a40000000.pcie: PCIe Gen.3 x4 link up [ 87.041138] rockchip-dw-pcie a40000000.pcie: Root Port reset completed [ 87.168378] pcieport 0000:00:00.0: Root Port has been reset [ 87.168882] rockchip-dw-pcie a40000000.pcie: PCIE_CLIENT_INTR_STATUS_MISC: 0x3 [ 87.169519] rockchip-dw-pcie a40000000.pcie: LTSSM_STATUS: 0x230011 [ 87.272463] rockchip-dw-pcie a40000000.pcie: Received Link up event. Starting enumeration! [ 87.277552] pcieport 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring [ 87.278314] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01 except that we don't get the: > [ 111.139686] pci-endpoint-test 0000:01:00.0: AER: can't recover (no > error_detected callback) > [ 111.384060] pcieport 0000:00:00.0: AER: device recovery failed prints. Kind regards, Niklas
