> -----Original Message----- > From: Manivannan Sadhasivam via B4 Relay > <devnull+manivannan.sadhasivam.oss.qualcomm....@kernel.org> > Sent: 2025年7月15日 22:21 > To: Bjorn Helgaas <bhelg...@google.com>; Mahesh J Salgaonkar > <mah...@linux.ibm.com>; Oliver O'Halloran <ooh...@gmail.com>; Will > Deacon <w...@kernel.org>; Lorenzo Pieralisi <lpieral...@kernel.org>; Krzysztof > Wilczy��ski <kwilczyn...@kernel.org>; Manivannan Sadhasivam > <m...@kernel.org>; Rob Herring <r...@kernel.org>; Heiko Stuebner > <he...@sntech.de>; Philipp Zabel <p.za...@pengutronix.de> > Cc: linux-...@vger.kernel.org; linux-ker...@vger.kernel.org; > linuxppc-dev@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org; > linux-arm-...@vger.kernel.org; linux-rockc...@lists.infradead.org; Niklas > Cassel <cas...@kernel.org>; Wilfred Mallawa <wilfred.mall...@wdc.com>; > Krishna Chaitanya Chundru <krishna.chun...@oss.qualcomm.com>; > m...@kernel.org; Lukas Wunner <lu...@wunner.de>; Manivannan Sadhasivam > <manivannan.sadhasi...@oss.qualcomm.com>; Manivannan Sadhasivam > <m...@kernel.org> > Subject: [PATCH v6 0/4] PCI: Add support for resetting the Root Ports in a > platform specific way > > [You don't often get email from > devnull+manivannan.sadhasivam.oss.qualcomm....@kernel.org. Learn why > this is important at https://aka.ms/LearnAboutSenderIdentification ] > > Hi, > > Currently, in the event of AER/DPC, PCI core will try to reset the slot (Root > Port) and its subordinate devices by invoking bridge control reset and FLR. > But in > some cases like AER Fatal error, it might be necessary to reset the Root Ports > using the PCI host bridge drivers in a platform specific way (as indicated by > the > TODO in the pcie_do_recovery() function in drivers/pci/pcie/err.c). > Otherwise, the PCI link won't be recovered successfully. > > So this series adds a new callback 'pci_host_bridge::reset_root_port' for the > host bridge drivers to reset the Root Port when a fatal error happens. > > Also, this series allows the host bridge drivers to handle PCI link down > event by > resetting the Root Ports and recovering the bus. This is accomplished by the > help > of the new 'pci_host_handle_link_down()' API. Host bridge drivers are expected > to call this API (preferrably from a threaded IRQ handler) with relevant Root > Port 'pci_dev' when a link down event is detected for the port. > The API will reuse the pcie_do_recovery() function to recover the link if AER > support is enabled, otherwise it will directly call the reset_root_port() > callback > of the host bridge driver (if exists). > > For reference, I've modified the pcie-qcom driver to call > pci_host_handle_link_down() API with Root Port 'pci_dev' after receiving the > LINK_DOWN global_irq event and populated > 'pci_host_bridge::reset_root_port()' > callback to reset the Root Port. Since the Qcom PCIe controllers support only > a > single Root Port (slot) per controller instance, the API is going to be > invoked only > once. For multi Root Port controllers, the controller driver is expected to > detect > the Root Port that received the link down event and call the > pci_host_handle_link_down() API with 'pci_dev' of that Root Port. > > Testing > ------- > > I've lost access to my test setup now. So Krishna (Cced) will help with > testing on > the Qcom platform and Wilfred or Niklas should be able to test it on Rockchip > platform. For the moment, this series is compile tested only. > > Changes in v6: > - Incorporated the patch: > https://lore.kern/ > el.org%2Fall%2F20250524185304.26698-2-manivannan.sadhasivam%40linaro.o > rg%2F&data=05%7C02%7Chongxing.zhu%40nxp.com%7C33c08e5bb14347e5c3 > cc08ddc3accaf5%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6388 > 81869083440222%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydW > UsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D > %7C0%7C%7C%7C&sdata=BsEibf7v8wAQzwt%2BbgozxE0Se8vvF9lb1O%2F0Hw > 1gG1M%3D&reserved=0 > - Link to v5: > https://lore.kern/ > el.org%2Fr%2F20250715-pci-port-reset-v5-0-26a5d278db40%40oss.qualcomm. > com&data=05%7C02%7Chongxing.zhu%40nxp.com%7C33c08e5bb14347e5c3c > c08ddc3accaf5%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63888 > 1869083460674%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUs > IlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D% > 7C0%7C%7C%7C&sdata=JVUK2udmAC4GCN6%2Bg%2B7rMVhnQWJXBF972JB2 > GJMrfWc%3D&reserved=0 > > Changes in v5: > * Reworked the pci_host_handle_link_down() to accept Root Port instead of > resetting all Root Ports in the event of link down. > * Renamed 'reset_slot' to 'reset_root_port' to avoid confusion as both terms > were used interchangibly and the series is intended to reset Root Port only. > * Added the Rockchip driver change to this series. > * Dropped the applied patches and review/tested tags due to rework. > * Rebased on top of v6.16-rc1. > > Changes in v4: > - Handled link down first in the irq handler > - Updated ICC & OPP bandwidth after link up in reset_slot() callback > - Link to v3: > https://lore.kern/ > el.org%2Fr%2F20250417-pcie-reset-slot-v3-0-59a10811c962%40linaro.org&dat > a=05%7C02%7Chongxing.zhu%40nxp.com%7C33c08e5bb14347e5c3cc08ddc3a > ccaf5%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6388818690834 > 74708%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLj > AuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C% > 7C%7C&sdata=vEVqdgjtUCGLMpEiUoMk5wdRNPAISlpXngguyA04Tu0%3D&rese > rved=0 > > Changes in v3: > - Made the pci-host-common driver as a common library for host controller > drivers > - Moved the reset slot code to pci-host-common library > - Link to v2: > https://lore.kern/ > el.org%2Fr%2F20250416-pcie-reset-slot-v2-0-efe76b278c10%40linaro.org&dat > a=05%7C02%7Chongxing.zhu%40nxp.com%7C33c08e5bb14347e5c3cc08ddc3a > ccaf5%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6388818690834 > 88340%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLj > AuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C% > 7C%7C&sdata=8BFu0YVMES1iBm649E0Ollz2Ju2ZEwuxB6%2BC%2F2sO19Q%3D > &reserved=0 > > Changes in v2: > - Moved calling reset_slot() callback from pcie_do_recovery() to > pcibios_reset_secondary_bus() > - Link to v1: > https://lore.kern/ > el.org%2Fr%2F20250404-pcie-reset-slot-v1-0-98952918bf90%40linaro.org&dat > a=05%7C02%7Chongxing.zhu%40nxp.com%7C33c08e5bb14347e5c3cc08ddc3a > ccaf5%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6388818690835 > 06149%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLj > AuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C% > 7C%7C&sdata=mbs8czUH0TzbZXD9zeUTPr1QyuCx8b%2BcYRhxUTXEjUQ%3D&r > eserved=0 > > Signed-off-by: Manivannan Sadhasivam > <manivannan.sadhasi...@oss.qualcomm.com>
[Richard Zhu] Tested-by: Richard Zhu <hongxing....@nxp.com> Tested this v6-series patches on i.MX95 platform. At least, the PCIe link can be re-established successfully although AER has some complains. Logs: <snipped> [ 32.563020] imx6q-pcie 4c300000.pcie: Stop root bus and handle link down [ 32.570025] pcieport 0000:00:00.0: Recovering Root Port due to Link Down [ 32.578213] pci 0000:01:00.0: AER: can't recover (no error_detected callback) [ 32.586536] pci 0000:01:00.1: AER: can't recover (no error_detected callback) [ 32.898399] imx6q-pcie 4c300000.pcie: PCIe Gen.2 x1 link up [ 33.030438] pcieport 0000:00:00.0: Root Port has been reset [ 33.036133] pcieport 0000:00:00.0: AER: device recovery failed [ 33.041991] imx6q-pcie 4c300000.pcie: Rescan bus after link up is detected [ 33.050135] pcieport 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring [ 33.058620] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01 <snipped> Best Regards Richard Zhu > --- > Manivannan Sadhasivam (3): > PCI/ERR: Add support for resetting the Root Ports in a platform specific > way > PCI: host-common: Add link down handling for Root Ports > PCI: qcom: Add support for resetting the Root Port due to link down > event > > Wilfred Mallawa (1): > PCI: dw-rockchip: Add support to reset Root Port upon link down event > > drivers/pci/controller/dwc/Kconfig | 2 + > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 91 ++++++++++++++++++- > drivers/pci/controller/dwc/pcie-qcom.c | 120 > ++++++++++++++++++++++++-- > drivers/pci/controller/pci-host-common.c | 33 +++++++ > drivers/pci/controller/pci-host-common.h | 1 + > drivers/pci/pci.c | 21 +++++ > drivers/pci/pcie/err.c | 6 +- > include/linux/pci.h | 1 + > 8 files changed, 260 insertions(+), 15 deletions(-) > --- > base-commit: 19272b37aa4f83ca52bdf9c16d5d81bdd1354494 > change-id: 20250715-pci-port-reset-4d9519570123 > > Best regards, > -- > Manivannan Sadhasivam <manivannan.sadhasi...@oss.qualcomm.com> > >
